Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-01-05
2002-02-05
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S305000
Reexamination Certificate
active
06344397
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to fabrication of integrated circuit devices, and, more particularly, to a method of forming a semiconductor device with improved electrical characteristics.
2. Description of the Related Art
In the field of semiconductor integrated circuit devices, the dimensions/sizes of various design features are being steadily decreased for a variety of reasons. For example, design feature sizes are being decreased to achieve higher packaging densities for improving device performance, and to improve electrical performance characteristics of the semiconductor devices, such as a field effect transistor.
Complex digital circuits, such as central processing units (CPUs) and the like, demand fast switching transistors. All other things, being equal, the shorter the channel length of a transistor, the faster it will operate. Accordingly, there is a constant drive to reduce the channel-length on modern transistor devices. For example, the longitudinal dimension of a gate electrode of a transistor, i.e., the gate width, may extend to 20 &mgr;m, whereas the distance between the drain and source, i.e., the channel length or gate length, may be reduced to 0.2 &mgr;m or below.
As the channel length has been reduced to obtain the desired switching characteristic, the length of the gate electrode has also been reduced. Since the gate electrode may only be electrically connected at one end, the electrical charges used to establish a transverse electrical field for forming the channel between the drain region and the source region of the transistor have to be transported along the entire width of the gate electrode. Given the small transverse dimension (length) of the gate electrode, the electrical resistance is relatively high, which may result in higher RC-delay time-constants. Hence, generation of the transverse electrical field used to fully open the channel is delayed, thereby deteriorating the switching time of the transistor. As a consequence, the rise and fall times of the electrical signals are increased and the operating frequency, i.e., the clock frequency, is reduced. Thus, the switching time of the transistor is no longer limited by the drain and source characteristics, but rather, significantly depends on the delay associated with signal propagation along the gate electrode, i.e., the transistor performance depends, at least in part, on the resistance of the gate electrode in the longitudinal direction of the gate electrode, i.e., in the gate width direction.
The manufacturing process of integrated circuits (ICs) involves the fabrication of numerous insulated gate field effect transistors, such as metal oxide semiconductor field effect transistors (MOSFET). There is a constant drive to continually reduce the feature sizes of the transistor structures to increase the integration density and improve device performance with respect to, for example, signal processing time and power consumption. Therefore, there is a demand for ever improved efficient, reliable and relatively inexpensive methods for patterning the structural features and layers in an integrated circuit device that are suitable for use in the mass production of such devices. Optical photolithography is generally used as a standard method for feature definition in such devices in mass production settings. Currently available photolithography steppers using high numerical aperture lenses and deep ultraviolet (UV) exposure light are, for instance, capable of reliably printing feature sizes as small as 0.2 &mgr;m.
The formation of the gate electrode is a critical step in the manufacturing process of a field effect transistor (“FET”). It is desirable that the gate length dimension, i.e., the lateral extension of the gate electrode between the source and drain electrodes of the FET, be reduced to sizes approaching or even exceeding the resolution limit of the optical imaging systems used for patterning the device features. In a field effect transistor, such as a MOSFET, the gate electrode is used to control an underlying channel formed in the semiconductor substrate between a source region and a drain region. Channel, source region, and drain region are formed in, on, or over a semiconductor substrate which is doped inversely to the drain and source regions. The gate electrode is separated from the channel, the source region and the drain region by a thin insulating gate dielectric layer, generally a layer comprised of silicon dioxide.
During operation, a voltage is supplied to the gate electrode to create an electric field between the gate electrode and the source and drain regions affecting conductivity in the channel region of the substrate beneath the gate conductor. Besides the desired transistor current control function, the gate electrode, the gate dielectric layer, and the regions underlying the gate dielectric layer also act as a capacitor. The amount of this parasitic capacitance depends on the feature size of the gate electrode. In many integrated circuit applications, the transistors are operated in a switching mode with clock frequencies currently as high as 400-600 MHz, and greater clock speeds are envisioned in the future. In this operation mode, the parasitic capacitance has to be continuously charged and discharged, which significantly affects signal performance and power consumption of the device.
An illustrative example of forming a gate electrode according to a typical prior art process will be described with reference to
FIGS. 1A-1C
. In
FIG. 1A
, shallow trench isolations
1
arc formed in a substrate
2
to define an electrically active region
30
in which a channel, drain and source regions are to be formed. Subsequently, a thin gate dielectric layer
3
comprised of silicon dioxide is grown by, for example, furnace processing. Then, a polysilicon layer
4
A is blanket-deposited, and a photoresist mask
5
is patterned on the polysilicon layer
4
A. The patterning of the photoresist mask
5
is typically performed by deep ultraviolet (DUV) photolithography, which is one method used to achieve the smallest feature dimensions of an integrated circuit device without compromising the required throughput. In a subsequent etching step, portions of the polysilicon layer
4
A are removed to form a gate electrode
4
(see FIG.
1
B).
FIG. 1B
is a cross-sectional view of the transistor structure after the photoresist mask
5
, portions of the polysilicon layer
4
A and the gate dielectric layer
3
have been removed. Subsequently, as shown in
FIG. 1C
, lightly doped drain (LDD) regions
8
are formed by an ion implantation process with a low dose of dopant material. The implanted dopant ions are diffused by rapid thermal annealing (RTA) so as to partially extend in the area below the gate dielectric layer
3
. With reference to
FIG. 1C
, sidewall spacers
6
are formed adjacent the gate electrode
4
by forming a layer of spacer material, e.g., silicon dioxide, and performing an anisotropic etching process. Next, a further implantation step with a higher dose of dopant atoms is performed to generate the final drain and source regions
7
.
In
FIG. 1C
, a transistor structure fabricated according to conventional methods is shown wherein the drain and source regions
7
are limited by lightly doped drain regions
8
, which connect to a channel
9
. The transverse dimension of the gate electrode
4
defines a gate length
10
. For the sake of clarity, the person skilled in the art will appreciate that the above mentioned processes are merely schematically described. In particular, those skilled in the art will understand that the DUV photolithographical step involves certain sub steps, such as providing an anti-reflecting coating, which are not specifically recited above.
As mentioned above, the gate length
10
is defined by the gate electrode
4
, which, in turn, is defined by the DUV photolithographical step and the subsequent etching of the layer from which the gate electrode
4
is formed. This can be problematic if the gate leng
Engelmann Bernd
Horstmann Manfred
Wieczorek Karsten
Advanced Micro Devices , Inc.
Le Dung A
Nelms David
Williams Morgan & Amerson P.C.
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