Semiconductor device having a fuse barrier pattern and...

Details Semiconductor device having a fuse barrier pattern and... Semiconductor device having a fuse barrier pattern and...

2006-04-10

2009-12-15

Coleman, W. David (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C257S529000

Reexamination Certificate

active

07632748

ABSTRACT:
In a semiconductor device having a plurality of fuses and a method of fabricating the same, the semiconductor device comprises an inter-layer dielectric layer on a semiconductor substrate; a plurality of fuses on the inter-layer dielectric layer, an inter-metallic dielectric layer on the plurality of fuses and the inter-layer dielectric layer, a passivation layer on the inter-metallic dielectric layer, fuse windows exposing portions of a top surface and sidewall surfaces of the plurality of fuses, and a fuse barrier pattern between adjacent ones of the plurality of the fuses.

REFERENCES:
patent: 4536949 (1985-08-01), Takayama et al.
patent: 5729041 (1998-03-01), Yoo et al.
patent: 2005/0236688 (2005-10-01), Bang et al.
patent: 08-172134 (1996-07-01), None
patent: 10-2002-0024460 (2002-03-01), None
patent: 10-2004-0008484 (2004-01-01), None

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