Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-09-10
2002-12-17
Meier, Stephen D. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S239000, C438S250000, C438S393000, C438S396000, C438S253000
Reexamination Certificate
active
06495412
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor devices and more particularly to a semiconductor memory device that uses a ferroelectric film.
Semiconductor devices such as DRAMs and SRAMs are used extensively in various information processing apparatuses including computers as a high-speed main memory device. These conventional semiconductor devices, however, are volatile in nature and the information stored therein is lost when the electric power is turned off. Thus, it has been practiced in conventional computers and computer systems to use a magnetic disk device as a large capacity, auxiliary storage device for storing programs and data.
However, magnetic disk devices are bulky and fragile, and are inherently vulnerable to mechanical shocks. Further, magnetic disk devices generally have drawbacks of large electrical power consumption and low access speed.
In view of the problems noted above, there is an increasing tendency in computers and computer systems of using flash-memory devices for the non-volatile auxiliary storage device. A flash-memory device is a device having a construction similar to a MOS transistor and stores information in a floating gate in the form of electrical charges. It should be noted that flash-memory devices have a construction suitable for monolithic integration on a semiconductor chip in the form of an LSI. Thus, there are attempts to construct a large-capacity storage device comparable to a magnetic disk device by using a flash-memory.
In a flash-memory device, writing of information is achieved by tunneling of hot electrons through a tunneling insulation film into the floating gate electrode. Further, erasing of the information is achieved also by causing the electrons in the floating gate to tunnel to a source region or to a channel region through the tunneling insulation film. Thus, a flash-memory device has an inherent drawback in that it takes a substantial time for writing or erasing information. Further, a flash-memory device generally shows the problem of deterioration of the tunneling insulation film after a repeated writing and erasing operations. When the tunneling insulation film is deteriorated, the reading or erasing operation becomes unstable and unreliable. An EEPROM, having a similar construction to a flash-memory, has a similar problem.
In view of the various drawbacks of the foregoing conventional non-volatile semiconductor devices, there is a proposal of a ferroelectric semiconductor memory device designated hereinafter as FeRAM for the auxiliary memory device and further for the high-speed main memory device of a computer. A ferroelectric semiconductor memory device stores information in a ferroelectric capacitor insulation film in the form of spontaneous polarization.
A ferroelectric semiconductor memory device typically includes a memory cell transistor and a memory cell capacitor similarly to a DRAM, wherein the memory cell capacitor uses a ferroelectric material such as PZT (Pb(Zr,Ti)O
3
) or PLZT ((Pb,La)(Zr,Ti)O
3
) for the capacitor insulation film. Thus, the ferroelectric semiconductor memory device is suitable for monolithic integration to form an LSI.
As the ferroelectric semiconductor memory device carries out the writing of information by controlling the spontaneous polarization of the ferroelectric capacitor insulation film, the writing is achieved with a high speed, faster by a factor of 1000 or more than in the case of a flash-memory. As noted before, the writing of information is achieved in a flash-memory by injecting hot electrons into the floating gate through the tunneling insulation film. As the control of the polarization is achieved by applying a voltage, the power consumption is also reduced below about {fraction (1/10)} as compared with the case of a flash-memory. Further, the ferroelectric semiconductor memory device, lacking the tunneling insulation film, provides an increased lifetime of one hundred thousand times as large as the lifetime of a flash-memory device.
Currently, FeRAMs are fabricated according to the relatively easy design rule of about 1 &mgr;m. On the other hand, investigation is being made for increasing the tightness of the design rule so as to enable integration of the FeRAMs with other high-speed submicron devices such as CMOS logic devices on a common semiconductor chip.
FIG. 1
shows the construction of a conventional FeRAM
10
.
Referring to
FIG. 1
, the FeRAM
10
includes a memory cell transistor constructed on a p-type Si substrate
11
, on which an active region is defined by a field oxide film
12
. On the Si substrate
11
, there is provided a gate electrode
13
in correspondence to the foregoing active region, wherein the gate electrode
13
constitutes the word line of the FeRAM. Further, a gate oxide film not illustrated is interposed between the Si substrate
11
and the gate electrode
13
, and diffusion regions
11
A and
11
B of the n
+
-type are formed in the substrate
11
at both lateral sides of the gate electrode
13
as the source region and the drain region of the memory cell transistor. Thereby, a channel region is formed in the substrate
11
between the diffusion region
11
A and the diffusion region
11
B.
It should be noted that the gate electrode
13
is covered by a CVD oxide film
14
provided so as to cover the surface of the Si substrate
11
in correspondence to the active region, wherein the CVD oxide film
14
is covered by a planarizing interlayer insulation film
15
. The interlayer insulation film
15
is formed with a contact hole
15
A exposing the diffusion region
11
B, and the contact hole
15
A is filled by a conductive plug
16
of polysilicon or WSi.
Further, there is provided an adhesion layer
17
having a Ti/TiN structure on the interlayer insulation film
15
so as to cover the exposed part of the plug
16
, and a lower electrode
18
of Pt is formed on the foregoing adhesion layer
17
. The lower electrode
18
is covered by a ferroelectric capacitor insulation film
19
of PZT or PLZT, and an upper electrode of Pt is formed on the ferroelectric capacitor insulation film
19
.
It should be noted that the lower electrode
18
, ferroelectric capacitor insulation film
19
and the upper electrode
20
form together a ferroelectric capacitor defined by a side wall, wherein the side wall is covered by a CVD oxide film
21
, and the ferroelectric capacitor as a whole is covered by another interlayer insulation film
22
.
The interlayer insulation film
22
is formed with a contact hole
22
A exposing the diffusion region
11
A, and there is provided a bit line pattern
23
of Al or an Al-alloy on the interlayer insulation film
22
so as to make an electrical contact with the diffusion region
11
A at the contact hole
22
A.
FIG. 2
shows the hysteresis appearing in the polarization of a PLZT film constituting the foregoing ferroelectric capacitor insulation film
19
.
Referring to
FIG. 2
, it will be noted that the PLZT film
19
experiences an inversion of polarization when a predetermined write voltage is applied between the lower electrode
18
and the upper electrode
20
such that a predetermined electric field is applied to the PLZT film
19
. In other words, desired information is written into the PLZT film
19
in the form of binary data by applying the write voltage across the upper electrode
20
and the lower electrode
18
. Further, the reading of the information thus written into the PLZT film
19
is achieved by detecting the conduction or no-conduction of the memory cell transistor, wherein such a detection is made by activating the foregoing word line, and hence the gate electrode
13
, and further by detecting the voltage appearing at the bit line electrode
23
.
Larger the value of the spontaneous polarization represented in
FIG. 2
by 2Pr, the more the reliability of the retention of information in the PLZT film
19
. Further, the magnitude of the electric field needed to cause a writing of information decreases with increasing value of 2Pr. In other words, increase
Noshiro Hideyuki
Takai Kazuaki
Yamauchi Hideaki
Zhu Sha
Armstrong Westerman & Hattori, LLP
Fujitsu Limited
Meier Stephen D.
Thomas Toniae M.
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