Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-09-07
2002-09-17
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S623000, C438S624000, C438S645000, C438S646000
Reexamination Certificate
active
06451684
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a conductive layer having a side surface slope of at least 90° and a method for manufacturing the same.
2. Description of the Related Art
Conventionally, the side surface slope of an insulating film pattern having a hole for forming a conductive layer using a dry etching method is greater than 90°. When a Damascene conductive layer is formed by performing a Damascene process using the insulating film pattern as a mask, the side surface slope of the formed Damascene conductive layer is smaller than 90°. When another adjacent conductive layer is formed in a subsequent process, a misalignment margin between two adjacent conductive layers is reduced. Thus, a short might be generated between the adjacent two conductive layers. Though the etching process is performed to insure a 90° side surface slope of the insulating film pattern, the side surface slope of the insulating film pattern often is greater than 90° after cleaning.
FIGS. 1A through 1E
are sectional views of a conventional method for manufacturing a semiconductor device having the Damascene conductive layer. First, as shown in
FIG. 1A
, a first insulating film
110
is formed on a semiconductor substrate
100
. Thereafter, a plug
120
is formed of a conductive material, such as polysilicon, between portions of the first insulating film
110
. A second insulating film
130
is formed on the first insulating film
110
and the plug
120
. As shown in
FIG. 1B
, a photoresist pattern
140
is formed on a second insulating film
130
by exposing and developing the second insulating film using conventional lithography. A second insulating film pattern
130
is formed by etching the second insulating film
130
using the photoresist pattern
140
as a mask thereby exposing the plug
120
(FIG.
1
C). Cleaning is then performed using a radio frequency (RF) etching method after removing the photoresist pattern
140
. In general, the second insulating film pattern
130
′ is formed by using a dry etching process. The side surface slope &agr;of the second insulating film pattern
130
′ formed is greater than 90°.
With reference to
FIG. 1D
, a conductive material
150
such as polysilicon or metal is deposited between portions of the second insulating film pattern
130
′. As shown in
FIG. 1E
, flattening the conductive layer
150
using a chemical mechanical polishing (CMP) method completes a Damascene conductive layer
150
′, In the CMP method, the upper surface of the second insulating film pattern
130
′ is used as an end point. The completed conductive layer
150
′ has a structure in which a side surface slope is less than 90°. Thus, the misalignment margin is reduced in a subsequent contact forming process increasing the risk of developing shorts between adjacent conductive layers. Accordingly, a need remains for a semiconductor device and a method for manufacturing the same in which the side surface slope of a conductive layer is at least 90° to thereby increase the misalignment margin.
SUMMARY OF THE INVENTION
It is an object of the present invention to overcome the problems associated with prior art semiconductor memory devices and methods for making the same.
It is another object of the present invention to provide a semiconductor device having a conductive layer that prevents the generation of a short between adjacent conductive layers.
It is yet another object of the present invention to provide a method for manufacturing a semiconductor device having a conductive layer that prevents the generation of shorts between adjacent conductive layer.
Accordingly, a semiconductor device is provided. The semiconductor device having a conductive layer according to the present invention comprises an interlayer dielectric film and a conductive layer on a semiconductor substrate. The interlayer dielectric film defines a hole and has a side surface slope of no more than 90°. The conductive layer formed in the hole defined by the interlayer dielectric film has a side surface slope of at least 90°.
The interlayer dielectric film pattern is preferably formed of a silicate on glass, a flowable oxide, an undoped silicate glass, a plasma enhanced-tetra ethyl ortho silicate, boron phosphorus silicate glass, or a high density plasma oxide. The conductive layer is preferably formed of doped polysilicon, W, WSi, Cu, Ti, TiN, Al, Pt, Ir, or Ru.
A method for manufacturing the above-described semiconductor memory device is also provided. A preliminary film is deposited on a semiconductor substrate. A preliminary film pattern the side surface slope of which is at least 90° is formed by patterning the preliminary film. An interlayer dielectric film is formed on the semiconductor substrate and the preliminary film pattern. The upper surface of the preliminary film pattern is exposed by removing some of the interlayer dielectric film. An interlayer dielectric pattern defining a hole and having a side surface slope of no more than 90° is formed by removing the preliminary film pattern. A conductive layer the side surface slope is at least 90° is formed by forming a conductive material in the hole.
The preliminary film is preferably formed using nitride silicon or polysilicon. The interlayer dielectric film is preferably formed using a flowable insulating material such as silicate on glass or flowable oxide.
Forming the interlayer dielectric film includes forming an unflowable insulating film. The method further includes forming a flowable insulating film on the interlayer dielectric film after forming the interlayer dielectric film and flattening the flowable insulating film. Removing some of the interlayer dielectric film and flowable insulating film exposes an upper surface of the preliminary film pattern.
The semiconductor device of the present invention prevents the generation of a short between a conductive layer formed in the hole and an adjacent conductive layer by increasing a misalignment margin during a subsequent process for forming the contact hole. In particular, when the conductive layer is used as a storage node of a capacitor, the coverage of a dielectric film is improved in a subsequent processing of forming a dielectric film by the CVD method.
REFERENCES:
patent: 5840619 (1998-11-01), Hayashide
patent: 6211051 (2001-04-01), Jurgensen
Kim Myeong-cheol
Yang Hee-sung
Berry Renee R.
Marger & Johnson & McCollom, P.C.
Nelms David
Samsung Electronics Co,. Ltd.
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