Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-05-04
2001-12-25
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S532000, C257S535000, C257S640000, C257S649000, C257S764000
Reexamination Certificate
active
06333528
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device having ferroelectric layer or high dielectric layer as capacitor dielectric layer and a manufacturing method thereof.
BACKGROUND OF THE INVENTION
Recently, along with the trend of higher speed and lower power consumption of semiconductor devices such as microcomputers and digital signal processors electronic appliances for consumer use are more and more advanced in performance, while an electromagnetic interference which is an electromagnetic noise generated from these electronic appliances is posing a serious problem. Accordingly, not only in electronic appliances, but also in semiconductor devices used in them, measures against electromagnetic interference are demanded. The most effective measure against electromagnetic interference in the semiconductor device is to install a capacitor of a large capacitance between the bias line and ground line inside the semiconductor device, hitherto the capacitor was placed outside the semiconductor device.
In addition, lately, nonvolatile random access memories in a simple construction having a capacitor, using a ferroelectric layer as a capacitor dielectric layer, and dynamic random access memories having a capacitors using dielectric layer of a high dielectric constant as storage capacitors have been developed.
A conventional semiconductor device having a capacitor is specifically described below.
FIG. 1
is a partially sectional view of a representative semiconductor device. In
FIG. 1
, on a silicon substrate
1
, an integrated circuit
6
represented by source/drain active areas
3
, a gate oxide
4
, and a gate electrode
5
is formed in a region enclosed by a filed oxide area
2
. Further on the silicon substrate
1
, an insulating layer
7
is formed, and in a specific region on the insulating layer
7
, a capacitor
11
consisting of a bottom electrode
8
, a capacitor dielectric layer
9
, and a top electrode
10
is formed. At least covering the capacitor
11
, moreover, an interlayer insulating layer
12
is formed. There are also formed interconnections
14
a
connected to the source/drain active areas
3
through a first contact hole
13
a,
interconnection
14
b
connected to the bottom electrode
8
of the capacitor
11
through a second contact hole
13
b,
and interconnection
14
c
connected to the top electrode
10
of the capacitor
11
through a third contact hole
13
c.
Furthermore, a passivation layer
15
is formed in order to protect the interconnections
14
a,
14
b,
14
c.
A manufacturing method of the conventional semiconductor device having capacitor shown in
FIG. 1
is explained below while referring to the flow chart of manufacturing process shown in
FIG. 2
, together with FIG.
1
. First, at step (1), the integrated circuit
6
is formed on the silicon substrate
1
. At step (2), an insulating layer
7
is formed on a silicon substrate
1
. At step (3), a capacitor
11
is formed on the insulating layer
7
. This capacitor
11
is formed by sequentially laminating a first conductive layer as bottom electrode
8
, capacitor dielectric layer
9
, and a second conductive layer as top electrode
10
, and patterning respectively by etching. As the capacitor dielectric layer
9
, a ferroelectric layer or high dielectric layer is used, and as bottom electrode
8
and top electrode
10
, a two-layer composition consisting of platinum layer and titanium layer sequentially from the side contacting with the capacitor dielectric layer
9
is used. At step (4), an interlayer insulating layer
12
composed of PSG (phospho-silicate glass) is formed by CVD so that at least the capacitor
11
is covered. At step (5), a first contact hole
13
a
reaching the source/drain active areas
3
of the integrated circuit
6
, a second contact hole
13
b
reaching the bottom electrode
8
of the capacitor
11
, and a third contact hole
13
c
reaching the top electrode
10
of the capacitor
11
are formed. After forming interconnections
14
a,
14
b,
14
c
at step (6), a passivation layer
15
composed of silicon nitride layer or silicon oxynitride layer of high humidity resistance is formed by plasma CVD at step (7).
However, in such conventional semiconductor device having capacitor, a PSG layer is used as interlayer insulating layer
12
, and although the purpose of alleviating the stress to the capacitor
11
is achieved, the moisture generated when forming the PSG layer by CVD is absorbed by the PSG layer, and this moisture diffuses into the ferroelectric layer comprising the capacitor dielectric layer, thereby lowering the electric resistance. This phenomenon gives rise to increase of leakage current of the capacitor
11
or decline of dielectric strength, which may induce dielectric breakdown of the capacitor dielectric layer
9
.
Yet, in such conventional semiconductor device having capacitor, as a passivation layer
15
, silicon nitride layer or silicon oxynitride layer formed by plasma CVD is used, and although invasion of moisture from outside into the capacitor
11
may be prevented, activated hydrogen is generated in the layer forming process by plasma CVD, and this activated hydrogen may diffuse in the ferroelectric layer or high dielectric layer for composing the capacitor dielectric layer
9
, which may induce increase of leakage current of the capacitor
11
or deterioration of electrical characteristics. Generally, the hydrogen atom content in the nitride layer formed by plasma CVD is as high as 10
22
atoms/cm
3
, and by heat treatment after layer forming, diffusion of hydrogen into the capacitor dielectric layer
9
is accelerated, and the characteristic of the capacitor
11
is further degenerated.
SUMMARY OF THE INVENTION
It is hence a primary object of the invention to present a semiconductor device having capacitor with high reliability. It is another object thereof to present a manufacturing method of such semiconductor device without deteriorating the integrated circuit formed on a semiconductor substrate.
In an embodiment of the semiconductor device of the invention, a capacitor consisting of bottom electrode, capacitor dielectric layer, and top electrode is formed on an insulating layer on a semiconductor substrate in which an integrated circuit is fabricated, and it is constituted that the moisture content in the interlayer insulating layer which covers this capacitor may not exceed 0.5 g as converted to 1 cm
3
of the interlayer insulating layer.
According to this constitution, diffusion of moisture into the capacitor dielectric layer can be suppressed, and lowering of dielectric strength of the capacitor dielectric layer can be prevented, and hence it has been confirmed that the reliability is enhanced.
In another embodiment of the semiconductor device of the invention, the passivation layer which covers the interconnections is constituted as a silicon nitride layer with the hydrogen atom content of 10
2 1
atoms/cm
3
or less.
In this constitution, if heated at around 400° C. after forming the silicon nitride layer, the number of hydrogen atoms diffusion into the capacitor dielectric layer is small, and it has been confirmed that characteristic deterioration of the capacitor does not occur.
In another embodiment of the semiconductor device of the invention, as the passivation layer which covers the interconnections, a PSG layer (phosphosilicate glass layer) and NSG layer (non-doped silicate glass layer) are laminated sequentially from the interconnection side.
According to the constitution, different from the silicon nitride layer or silicon oxynitride layer formed by the conventional plasma CVD, since hydrogen is not contained in the passivation layer, the capacitor dielectric layer will not deteriorate. Besides, the stress relaxation on the capacitor can be prevented by the PSG layer, and the moisture absorption which is a demerit of the PSG layer can be prevented by the NSG layer formed thereon, so that stress may not be applied on the capacitor, thereby realizing a high reliability.
In a different embodiment of
Arita Koji
Fujii Eiji
Inoue Atsuo
Matsuda Akihiro
Matsuura Taketoshi
Loke Steven
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
LandOfFree
Semiconductor device having a capacitor exhibiting improved... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having a capacitor exhibiting improved..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having a capacitor exhibiting improved... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2593121