Electronic digital logic circuitry – Significant integrated structure – layout – or layout... – Field-effect transistor
Reexamination Certificate
1999-10-12
2001-04-17
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Significant integrated structure, layout, or layout...
Field-effect transistor
C326S101000, C326S136000
Reexamination Certificate
active
06218866
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and, in particular, to devices for the prevention of a floating gate condition in MOS logic circuits and processes for their manufacture.
2. Description of the Related Art
Referring to
FIG. 1
, a conventional Metal-Oxide-Semiconductor (MOS) logic circuit in the form of an inverter
10
is illustrated. Inverter
10
includes interconnected MOS transistors
12
and
14
, and is capable of producing an output state (e.g., an output voltage) at the output node
16
in response to an input state (e.g., an input voltage) applied at the input node
18
. The input node
18
is connected to the gates of the MOS transistors
12
and
14
. In other words, the gates of these MOS transistors
12
and
14
are connected to each other to serve as the input node
18
. For a further explanation of MOS inverters, see S. Wolf,
Silicon Processing for the VLSI Era, Vol.
2—
Process Integration,
373-376 (Lattice Press, 1990), which is hereby fully incorporated by reference.
Input node
18
is referred to as a “floating gate” since there is no electrical connection between the input node
18
(which is made up of the connected gates of MOS transistors
12
and
14
) and either ground (GND) or the power supply voltage (V
DD
). In this regard, the term “floating gate” refers to the fact that the input state (i.e., input voltage) on the input node
18
and, therefore on the gates of the MOS transistors
12
and
14
, is undefined and unknown. As a result, the output state produced by the inverter
10
at output node
16
is also undefined and unknown. Such an undesirable “floating gate” condition on the input node of an MOS logic circuit can be prevented by providing an electrical connection between the input node and either GND or V
DD
. Conventional semiconductor devices for this purpose can take the form of: (i) a resistor
20
connected between input node
18
of the MOS logic circuit and GND, as shown in
FIG. 2
; and (ii) an MOS transistor
30
with its gate connected to V
DD
, while its source is connected to input node
18
of the MOS logic circuit and its drain is connected to GND, as shown in FIG.
3
.
The operation of conventional MOS logic circuits requires that a well defined logic state of either “0” or “1” be generated and applied to the input node of the MOS logic circuit by driving circuitry included within the MOS logic circuit. For example, a “0” or “1” logic state can be generated from the output node of another inverter or other MOS logic element. A logic state of “0” represents a voltage of essentially zero volts (e.g., GND or V
SS
) and is commonly referred to as a “low” state. A logic state of “1” represents a voltage of a magnitude significantly greater than that of the logic state of “0”. The logic state of “1” is typically equal to V
DD
, and is generally referred to as a “high” state. If neither of these well defined logic states is applied to the input node of a MOS logic circuit, the input node of the MOS logic circuit can assume a random ambiguous state (i.e., an undefined state), thereby generating a random output state.
FIG. 4
illustrates an MOS logic circuit
40
wherein an inverter
42
is connected via its input node
44
to the output node
46
of driving circuitry
48
(which is illustrated for the purposes of this description as an MOS inverter). The input node
44
of inverter
42
and the output node
46
of driving circuitry
48
are also electrically connected to GND via resistor
50
. A drawback of this configuration is that current is constantly consumed when the driving circuitry
48
is imposing a high logic state on the input node
44
of inverter
42
. The path of this current consumption is shown by the dashed arrow in FIG.
4
.
Still needed in the art is a semiconductor device that is capable of preventing a “floating gate” condition on an input node of a MOS logic circuit. The semiconductor device should also provide for reduced power consumption when the input mode of the MOS logic circuit is driven to a high state by driving circuitry. Also needed is a process for its manufacture that is simple and compatible with standard semiconductor device processing.
SUMMARY OF THE INVENTION
The present invention provides a semiconductor device that prevents a floating gate condition on the input node of an MOS logic circuit. Semiconductor devices according to the present invention provide a near “short circuit” (i.e., a low impedance resistive path) between the input node of an MOS logic circuit (for example, a CMOS NOT gate, NOR gate, NAND gate, or CMOS logic circuits associated with embedded memory circuits) and GND (e.g., V
SS
) when an input signal to the input node of the MOS logic circuit is “low” (e.g., the input node is at low state) or undefined. Semiconductor devices according to the present invention also isolate the input node of the MOS logic circuit from GND when the input signal to the input node is driven “high” (e.g., the input node is at high state) by driving circuitry included within the MOS logic circuit. Therefore, semiconductor devices according to the present invention prevent a floating gate condition from occurring on the input node of an MOS logic circuit.
Semiconductor devices in accordance with the present invention include a semiconductor substrate of a first conductivity type (typically p-type) with an active area on its surface and a vertically integrated pinch resistor formed in the semiconductor substrate. The vertically integrated pinch resistor includes a deep well region of a second conductivity type (typically n-type) disposed below both the semiconductor substrate surface and the active area, as well as a first surface well region of the second conductivity type (e.g., n-type) disposed on the semiconductor substrate. The first surface well region circumscribes (i.e., encircles) both the deep well region and the active area of the semiconductor substrate, thereby forming a narrow channel region of the first conductivity type (e.g., p-type) in the semiconductor substrate. This narrow channel region separates the deep well region from the first surface well region.
The vertically integrated pinch resistor also includes a first contact region in the first surface well region, a second contact region in the active area, and a third contact region in the semiconductor substrate. The first and second contact regions are capable of being electrically connected to the input node of the MOS logic circuit, while the third contact region is capable of being electrically connected to ground. This structural configuration provides for the input node of the MOS logic circuit to be electrically connected to ground via a low impedance resistive path through the vertically integrated pinch resistor. This structural configuration, therefore, prevents the input node from acquiring a floating gate condition and forces a well defined logic state of “0” on the input node.
In the circumstance where the MOS logic circuit includes driving circuitry, the first contact region and second contact region are also capable of being electrically connected to an output node of the driving circuitry. This structural configuration provides for the input node of the MOS logic circuit to be electrically connected to ground (via a low impedance resistive path through the vertically integrated pinch resistor) when a logic state of “0” or an undefined logic state is applied to the first and second contact regions from the output node of the driving circuitry. Such a connection to ground prevents the input node from acquiring a floating gate condition and forces a well defined logic state of “0” on the input node. However, when a logic state of “1” (i.e., a “high” state, typically a voltage equal to V
DD
) is applied to the first and second contact regions from the output node of the driving circuitry, the low impedance resistive path is pinched-off due to formation of a depletion region in the narrow channel region of the vertically integrated pinch r
Kalnitsky Alexander
Poplevine Pavel
National Semiconductor Corporation
Pillsbury & Winthrop LLP
Tokar Michael
Tran Anh Q.
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