Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-05-09
2006-05-09
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S648000, C438S675000
Reexamination Certificate
active
07041594
ABSTRACT:
A first conduction type well is formed in a substrate, and a second conduction type impurity region is formed in the well. A lower interlayer dielectric is formed on the substrate, including the well and the impurity region. A contact plug, connected to the impurity region through the lower interlayer dielectric, is formed with a void inside it. An upper interlayer dielectric is formed on the lower interlayer dielectric and the contact plug. The upper interlayer dielectric is selectively etched, forming an interconnection groove exposing the contact plug. The contact plug and the exposed void are overetched, extending the void into the first conduction type well. The interconnection groove is filled with a conductive layer, forming an interconnection. A seam extending to the well is formed in the void, connecting the contact plug to the well. Due to the seam, a well bias may be applied to the well.
REFERENCES:
patent: 6534664 (2003-03-01), Guram et al.
patent: 2002/0125577 (2002-09-01), Komada
patent: 2003/0003727 (2003-01-01), Matsubara
patent: 2003/0008498 (2003-01-01), Nakata
Kim Young-Ok
Park Soon-Byung
Cao Phat X.
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
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