Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-05-13
2008-05-13
Kerveros, James C. (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
11305230
ABSTRACT:
A memory-logics LSI device forms an input/output path for testing. A memory device has a memory input/output unit,which includes an input/output selector with test function. A test clock signal, which is directly supplied in the test mode, is used to selectively take in one of input signals and an output signal to output the signal. The output is monitored on an external pin, while changing the timing of the positive-going edge of the clock signal, or the input signals. Relative measurement is then made on a delay amount indicating to which extent the input signals are delayedto cause a phase shift with respect to the clock signal,at the timing immediately before input to and after output from the memory device.
REFERENCES:
patent: 6415403 (2002-07-01), Huang et al.
patent: 6438720 (2002-08-01), Boutaud et al.
patent: 7007215 (2006-02-01), Kinoshita et al.
patent: 05-264675 (1993-10-01), None
patent: 11-174121 (1999-07-01), None
patent: 2002-162444 (2002-06-01), None
Mizuhashi Hiroshi
Yamamoto Toyoaki
Kerveros James C.
Studebaker Donald R.
LandOfFree
Semiconductor device for accurate measurement of time... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device for accurate measurement of time..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device for accurate measurement of time... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3944368