Semiconductor device fabrication with reduced masking steps

Details Semiconductor device fabrication with reduced masking steps Semiconductor device fabrication with reduced masking steps

1997-04-28

2000-04-04

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438138, 438268, 438270, 438530, H01L 21336

Patent

active

060460784

ABSTRACT:
A method of forming a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device on a semiconductor substrate with reduced masking steps is disclosed. In the first method, the reduced masking steps are arranged in an optimal sequence in which the gate layer is patterned first as a self-aligned mask. The gate layer includes a plurality of gate segments separated by spacings. An active mask for defining active body regions is then patterned in the spacings of the gate layer to form a combination mask. Using the combination mask as a shield, body and source regions are ion-implanted into the substrate. During the formation of the active mask, remnant material of the active mask adheres to the boundaries of the gate segments to form a spacer layer which is utilized to alleviate the cell-to-cell encroachment problem due to the side diffusion effect of the body and source regions. In the second method, trenched gates are formed first on the semiconductor substrate prior to the patterning of the active mask which is used to perform multiple duties of defining the source and body diffusions, and the delineation of the active circuit region from the termination circuit region of the MOSFET device.

REFERENCES:
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patent: 5194394 (1993-03-01), Terashima
patent: 5340756 (1994-08-01), Nagayasu
patent: 5387528 (1995-02-01), Hutchings et al.
patent: 5404040 (1995-04-01), Hshieh et al.
patent: 5656520 (1997-08-01), Watanabe
patent: 5668026 (1997-09-01), Lin et al.

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