Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-12-13
2002-07-16
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C700S105000, C700S120000, C700S121000, C700S103000, C430S005000, C378S035000, C382S144000
Reexamination Certificate
active
06421820
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices and photomasks and more particularly to a method of adding assist features to a photomask and integrated circuits formed using such a photomask.
BACKGROUND OF THE INVENTION
The manufacture of semiconductor devices is heavily dependent on the accurate replication of computer-aided-design (CAD) generated patterns onto the surface of a device substrate. The replication process is typically performed using optical lithography followed by a variety of subtractive (e.g., etch) and additive (e.g., deposition) processes. Optical lithography patterning involves the illumination of a metallic coated quartz plate known as a photomask which contains a magnified image of the computer generated pattern to be etched into the metallic layer. This illuminated image is reduced in size and patterned into a photosensitive film on the substrate.
As a result of the interference and processing effects which occur during pattern transfer, images formed on the substrate deviate from their ideal dimensions and shape as represented by the computer images. These deviations depend on the characteristics of the patterns as well as on a variety of process conditions. Because these deviations can significantly effect the performance of the semiconductor device, many approaches have been pursued which focus on CAD compensation schemes which ensure a resultant ideal image.
One such compensation scheme utilizes the selective biasing of mask patterns to compensate for the pattern distortions occurring during wafer processing. The term Optical Proximity Correction (OPC) is commonly used to describe this process of selective mask biasing, even though the trend exists to include pattern distortions unrelated to the optical image transfer. The idea of biasing patterns to compensate for image transfer infidelities has been commonly applied to E-beam lithography to counteract the effects of back scattered electrons, both in the writing of photo masks and in direct wafer writing operations.
Another known compensation technique is to add assist features, otherwise known as scattering bars or intensity leveling bars, to the photomask. Assist features are sub-lithographic features placed adjacent to a feature that is to be printed. Since these additional features are sub-lithographic, they will not be transferred to the resist during printing. They will, however, aid in sharpening the image that is printed.
It is well known that adding assist features to a photomask can help to improve the process window for printing isolated features. It is also known that the number of assist features that should be placed in the space between two critical features and the size of the assist features should be adjusted depending on the spacing between the critical features, among other things. What is not well known, however, is how to determine the optimum sizes and spacings for assist features in a real design containing critical features of varying size and a continuum of spacings between critical features. This task is complicated by the random nature and large data sizes of semiconductor designs.
At this point in time, commercially available software packages have taken two approaches to assist feature generation. The first (e.g., ASML MaskTools) is a straight rules based approach, where a simple set of assist feature design rules are used to generate assist features, along with applying rules based OPC to critical features. The second approach (e.g., Avant!) is to try to improve upon the rules based corrections, by using iterative model based corrections to the critical features after the assist features have been added. The problems with both of these approaches is that they are based on a simple rules based addition of the assist features, where generally up to two assist features can be added in the space between the two critical features. More than two assist features have been demonstrated but only at a fixed spacing between the critical feature and assist features.
SUMMARY OF THE INVENTION
In one aspect, the present invention provides an assist feature design method that is robust enough to handle varying critical feature sizes and a continuum of spacings between critical features. This method is also a computationally efficient rules-based approach that is capable of adding the correct number and size assist features to all spaces, including those bordered by line-end serifs or anchors. The assist feature design generation tool of the preferred embodiment is also robust enough to handle a wide variety of designs and also computationally efficient enough to be able to correct an entire chip in a reasonable amount of time.
In one aspect, the present invention provides a method of manufacturing a semiconductor device. Before the device can be fabricated, a layout of original shapes is designed. This layout represents elements (e.g., metal or polysilicon lines, areas to be etched) that are to be incorporated into the semiconductor device. For at least some, and preferably all, of the original shapes, the width of the shape and a distance to at least one neighboring shape are measured.
A modified shape can then be generated by moving edges of the original shape based on the width and distance measurements. This modification can be performed on some or all of the original shapes.
For each of the modified shapes, a distance between the modified shape and at least one neighboring shape is measured. A normalized space count can then be determined by dividing the measured distance by a normalized space constant and taking the integer value. The normalized space count can be used to determine a correct number of assist features and a normalized space. For example, the correct number of assist features can be determined by subtracting one from the normalized space count. The normalized space can be determined by dividing the measured distance by the normalized space count.
The layout is then modified by adding the correct number of assist features in a space between the modified shape and the neighboring shape. This modified layout can then be used in producing a photomask. The photomask can in turn be used to produce a semiconductor device.
In developing the preferred embodiment of the present invention, we have shown that simple rules based assist placement approaches are inadequate. For more isolated lines, several assist features are preferably used, and, for lines that have had serifs added to their ends, less assist features may be required at the line ends than over the rest of the line length. Although the iterative approach can help to improve feature uniformity and can better account for line-end effects, this approach does not always improve the process latitude to print these features, because it does not allow the addition or subtraction of assist features.
The preferred method of the present invention that applies OPC and adds assist features to a photomask design is both accurate and efficient. Its efficiency, or speed, is derived from using a rules based approach to determine the design modifications. Its accuracy is due to its ability to add various numbers of assist features with varying sizes and locations to a design. In this method, the photomask design is modified by a software tool that we will call the correction routine.
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pat
Butt Shahid
Haffner Henning
Liebmann Lars W.
Mansfield Scott M.
Braden Stanton
Infineon - Technologies AG
Kik Phallaka
Smith Matthew
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