Semiconductor device fabrication methods

Details Semiconductor device fabrication methods Semiconductor device fabrication methods

2008-04-29

2008-04-29

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S424000, C438S435000, C438S221000, C257S501000, C257SE21546, C257SE21548

Reexamination Certificate

active

11490301

ABSTRACT:
Methods of fabricating semiconductor devices are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece including a plurality of active area regions defined therein, and forming at least one trench in the workpiece between at least two of the plurality of active area regions. A first insulating material is deposited over the plurality of active area regions and the at least one trench, partially filling the at least one trench with the first insulating material and forming peaks of the first insulating material over the plurality of active area regions. A masking material is formed over the first insulating material in the at least one trench, leaving the peaks of the first insulating material over the plurality of active area regions completely exposed. At least the peaks of the first insulating material are removed from over the plurality of active area regions.

REFERENCES:
patent: 5480763 (1996-01-01), Kondo et al.
patent: 6171896 (2001-01-01), Jang et al.
patent: 6171962 (2001-01-01), Karlsson et al.
patent: 6210846 (2001-04-01), Rangarajan et al.
patent: 6251783 (2001-06-01), Yew et al.
patent: 6265302 (2001-07-01), Lim et al.
patent: 6531377 (2003-03-01), Knorr et al.
patent: 6667223 (2003-12-01), Seitz
patent: 6821865 (2004-11-01), Wise et al.
patent: 6914015 (2005-07-01), Belyansky et al.
patent: 7163869 (2007-01-01), Kim et al.
patent: 7244658 (2007-07-01), Yieh et al.
patent: 7279377 (2007-10-01), Rueger et al.
patent: 2001/0049179 (2001-12-01), Mori
patent: 2003/0013271 (2003-01-01), Knorr et al.
patent: 2005/0095872 (2005-05-01), Belyansky et al.
patent: 2007/0026629 (2007-02-01), Chen et al.
patent: 2007/0037341 (2007-02-01), Rueger et al.
Gruening, U., et al., “A Novel Trench DRAM Cell with a VERtIcal Access Transistor and BuriEd STrap (VERI BEST) for 4Gb/16Gb,” 1999, 4 pp., IEEE, Los Alamitos, CA.
Kersch, A., et al., “Recent Advances in Feature Scale Simulation,” IEDM, 2000, pp. 503-506, IEEE, Los Alamitos, CA.
Radens, C.J., et al., “An Orthogonal 6F2Trench-Sidewall Vertical Device Cell for 4Gb/16Gb DRAM,” 2000, 4 pp., IEEE, Los Alamitos, CA.

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