Semiconductor device fabrication method

Details Semiconductor device fabrication method Semiconductor device fabrication method

2007-01-30

2007-01-30

Dang, Phuc T. (Department: 2818)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S618000

Reexamination Certificate

active

11037110

ABSTRACT:
A method of performing microfabrication using a hard mask in the manufacture of a semiconductor device having an interlayer dielectric (ILD) film made of low-dielectric constant, K, insulating material is provided. When treating a low-K dielectric film for use in semiconductor integrated circuitry and its underlying etching stopper film, a patterned resist film is used as a mask to etch a hard mask film. Subsequently, the resist pattern is subjected to stripping or “ashing” in the atmosphere of a mixture gas of hydrogen (H2) and helium (He) at a temperature higher than 200° C. under a pressure of about 1 Torr. With this procedure, microfabrication relying upon the hard mask less in facet is achievable during its subsequent etching of the low-K dielectric film, without damaging the hard mask film upon removal of the resist.

REFERENCES:
patent: 6191031 (2001-02-01), Taguchi et al.
patent: 6506692 (2003-01-01), Andideh
patent: 6737350 (2004-05-01), Akahori et al.
patent: 6806203 (2004-10-01), Weidman et al.
patent: 7015133 (2006-03-01), Su et al.
patent: 2003/0032300 (2003-02-01), Waldfried et al.
patent: 2004/0084412 (2004-05-01), Waldfried et al.
patent: 2004/0235239 (2004-11-01), Inukai et al.
patent: 2005/0110153 (2005-05-01), Wu et al.
patent: 1276147 (2003-01-01), None
patent: 1385201 (2004-01-01), None
patent: 2855324 (2004-11-01), None
patent: 2001-203194 (2001-07-01), None
patent: 2004-87744 (2004-03-01), None
patent: WO 01/29879 (2001-04-01), None
patent: WO 01/59825 (2001-08-01), None
Furukawa et al., “Etch and strip induced material modification of porous low-K (K=2.2) dielectric,” Microelectronic Engineering 76(1-4):25-31, Oct. 2004.
Ohashi et al., “Robust Porous MSQ (k=2.3, E=12 GPa) for Low-temperature (<350°C.) Cu/Low-k Integration using ArF Resist Mask Process,” Int'l Electron Devices Meeting 2003. IEDM. Technical Digest, Washington, DC, Dec. 8-10, 2003, New York, NY: IEEE, US, Dec. 8, 2003, pp. 857-860, XP010684210.
Blaschta et al, “SiO2aerogel ultra low k dielectric patterning using different hard mask concepts and stripping processes, ” Microelectronic Engineering 76(1-4):8-15, Oct. 2004.

Affiliated with

Also associated with

Rating

Semiconductor device fabrication method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device fabrication method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device fabrication method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3776084