Semiconductor device fabrication method

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S287000, C438S763000, C438S765000, C438S792000

Reexamination Certificate

active

06960502

ABSTRACT:
A reduction of a leakage current as well as a decrease in the thickness of an insulating film is realized in a semiconductor device. To this end, a silicon oxide film and a silicon nitride film are formed on a substrate, which is then heated to a temperature within a range of 20° C.–600° C. so that a plasma nitridation process can be performed on the silicon nitride film. Further, a thermal process is performed in a non-oxide gas atmosphere. By performing these processes, the gate leakage current can be significantly reduced in the formed gate insulator, and the silicon oxide-equivalent thickness of the insulating film can be significantly decreased as well.

REFERENCES:
patent: 5962344 (1999-10-01), Tu et al.
patent: 6150226 (2000-11-01), Reinberg
patent: 6245652 (2001-06-01), Gardner et al.
patent: 6387761 (2002-05-01), Shih et al.
patent: 6403420 (2002-06-01), Yang et al.
patent: 6451662 (2002-09-01), Chudzik et al.
patent: 6504173 (2003-01-01), Hsu et al.
patent: 6544900 (2003-04-01), Raaijmakers et al.
patent: 2002/0124867 (2002-09-01), Kim et al.
patent: 2003/0157771 (2003-08-01), Luoh et al.
Wu et al., “Improvement of Gate Dielectric Realiabiltiy for p+ Poly MOS Devices Using Remote PECVD TOP Nitride Deposition on Thin Gate Oxides”, Mar. 31-Apr. 2, 1998, IEEE International, 36thAnnual International Reliability Physics Symposium, pp. 70-75.
Wu, Yider, “The Performance and Reliability of PMOSFET's with Ultrathin Silicon Nitride/Oxide Stacked Gate Dielectrics with Nitrided Si—SiO2 . . . Rapid Thermal Annealing”, IEEE Transactions oon Electron Devices, vol. 47, No. 7, Jul. 2000, pp. 1361-1369.
2001 Symposium on VLSI Technology, session T7A-4, Y. Yasuda et al., “Radical Nitridation in Multi-oxide Process for 100nm Generation CMOS Technology”, Kyoto, Japan, Jun. 12-14, 2001, pp. 83-84/Discussed in the specification.

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