Semiconductor device fabricating method

Details Semiconductor device fabricating method Semiconductor device fabricating method

2001-08-29

2002-10-22

Whitehead, Jr., Carl (Department: 2822)

Electrical connectors

Having retainer or passageway for fluent material

Liquid retainer

C438S221000, C438S224000, C438S225000, C438S228000, C438S275000, C438S981000, C438S425000

Reexamination Certificate

active

06468099

ABSTRACT:

1. FIELD OF THE INVENTION
The present invention relates to a method of fabricating a semiconductor device by which a thickness of an oxide film is prevented from being relatively thinned at the boundary between a shallow trench isolation and a thick gate oxide film when a process of fabricating a dual gate oxide is applied to a normal shallow trench isolation.
2. DESCRIPTION OF THE RELATED ART
Since power devices such as a liquid crystal display (LCD) driver IC (LDI) require both low voltage (LV) operation for driving an associated logic circuit, together with high voltage (HV) operation for driving the LCD during operation, associated gate oxide films are formed of a dual gate type. Also, the continuous trend toward ever-miniaturized line width requires the use of a shallow trench isolation (STI) process.
However, if the process for fabricating the dual gate oxide film is conducted in the same manner as it is applied to the STI structure, excessive numbers of STI recesses in the LV region are created during formation of the dual gate oxide film for the HV region, resulting in compromise of the overall device characteristics.
The source of the recesses lies in that since a CVD oxide film such as USG or HDP is used as a gap fill in the STI structure, and since a thermal oxide film is used as a gate oxide film, a severe dent is created in the boundary between the active region and the field region due to the difference in wet etch rate between the thermal oxide film and CVD oxide film.
This conventional process is explained in greater detail with reference to
FIGS. 1
a
through
1
c,
which illustrate the process of fabricating the conventional dual gate oxide film.
For convenience' sake, the process is explained by being classified into 3 steps as follows.
In the drawings, reference symbol “I” indicates a first active region in which a thin gate oxide film for LV is formed and reference “II” indicates a second active region in which a thick gate oxide film for HV is formed.
First Step
As shown in
FIG. 1
a
, a nitride film pattern (not shown) is formed in the first and second active regions I, II of the substrate
10
. The silicone substrate
10
is selectively etched to a predetermined thickness by using the pattern as mask so that trench (t) is formed in the field region within the substrate
10
. The CVD oxide film of USG or HDP material is formed on the resultant material so that the trench (t) is sufficiently filled. Next, the CVD oxide film is chemically mechanically polished so that the nitride pattern in the first and second active regions I, II may remain and thereafter the nitride film is removed. The STI
12
that buries the inside of the trench (t) is thus formed. Subsequently, CMOS well ion-implantation and channel ion-implantation are performed. The first thermal oxide film
14
for HV is subsequently formed to a thickness of 300 Å in the active regions I, II on the substrate
10
.
Second Step
As shown in
FIG. 1
b,
a photo-resist pattern
16
is formed on the resultant structure so that the first active region I and the surrounding STI
12
are partially exposed. The first thermal oxide film
14
is wet etched using the pattern as a mask and selectively remains only in the HV region II.
Third Step
As shown in
FIG. 1
c,
the photo-resist pattern
16
is removed and the second thermal oxide film
18
for LV is formed to a thickness of 40 Å in the first active region I. Thereby, the process for the dual gate oxide film is completed. In this process, when the second thermal oxide film
18
is formed, the first thermal oxide film
14
also grows to a small degree. However, since the amount of the growth is minor, the resultant effect is negligible.
As a result, the first active region I is formed therein with a relatively thin gate oxide film of the second thermal oxide film
18
material, which is suitable for the LV region. The second active region II is formed therein with a relatively thick gate oxide film of the first thermal oxide film
14
material, which is suitable for an HV region.
However, if the dual gate oxide film is formed through the aforementioned processes, a number of limitations result during the formation of device.
When the first thermal oxide film
14
of LV region I is removed by using the photo-resist pattern
16
as a mask, the STI
12
, which is indicated by â in
FIG. 1
b,
surrounding the perimeter of the LV region is recessed together with the first thermal oxide film
14
. Accordingly, a dent is generated in the region, that is, in the region of the boundary surface between the active region and the field region.
FIG. 2
shows the structure of a device having such defect.
Such a defect phenomenon is caused by the difference in a wet etch rate between the first thermal oxide film
14
being used as a gate oxide film and the CVD oxide film forming the STI
12
. For example, in the case where the STI
12
is filled with a HDP material, the depth of recess is approximately 200 Å relative to the substrate
10
of the active region. In contrast, in the case where the STI
12
is filled with a USG material, the recess amounts to approximately 1,000 Å relative to the substrate
10
of the active region, thereby the dent is more severely created.
In the case where the dent is formed, poly residue remains in the region that is recessed during etching of the gate poly as a follow up process, or the gate poly surrounds the field region and the active region at the boundary between the field region and the active region. Each of these scenarios results in deterioration in the gate oxide film due to the concentration of electric field created in upward and sideward directions as well as deterioration in characteristics such as drop in threshold voltage Vth of a resulting transistor during the operation of device, increase in threshold voltage leakage, and decrease in punching margin.
In order to solve those problems, there has been disclosed a process technique by which a dual gate oxide film is formed using a nitride film without the need for removing the thick thermal oxide film of the LV region while the process of fabricating the dual gate oxide film is applied to a normal STI structure in LDI design.
FIGS. 3
a
through
3
e
sequentially illustrate a sequence of forming a dual gate oxide structure. The method comprises five steps as follows.
Reference symbol “I” indicates a LV region in which a relatively thin gate oxide film is formed, and reference symbol “II” indicates a HV region in which a relatively thick gate oxide film is formed.
First Step
As shown in
FIG. 3
a,
the STI
102
of the CVD oxide film material that buries the inside of the trench (t) is formed in the field region on the silicone substrate
100
by the same method as shown in
FIG. 1
a.
The buffer oxide film
104
of the thermal oxide film material is subsequently formed in the active regions I, II on the substrate
100
and CMOS well ion-implantation and channel ion-implantation are performed. While the buffer oxide film
104
remains, the nitride film
106
is formed on the buffer oxide film
104
including the STI
102
. Thereafter, the CVD oxide film
108
of medium temperature oxide (MTO) is formed on the resultant material. Here, the MTO refers to an oxide film that is formed at the temperature of 700 to 800° C. The buffer oxide film
104
is formed at a thickness of 100 to 120 Å, the nitride film
106
is formed at a thickness of 90 to 110 Å and the CVD oxide film
108
is formed at a thickness of 90 to 110 Å.
Second Step
As shown in
FIG. 3
b,
the CVD oxide film
108
is patterned by a photo-resist pattern
110
so that the first active region I and the surrounding STI
102
are partially masked. The second active region II and the adjacent CVD oxide film
108
are wet etched with the pattern
110
as a mask.
During the third step shown in
FIG. 3
c,
the photo-resist pattern
110
is removed.
During the fourth step shown in
FIG. 3
d,
the nitride film
106
and the buffer oxide film
104
are in order etched by

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