Semiconductor device employing an extension spacer and a...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S384000, C257SE29266

Reexamination Certificate

active

10989073

ABSTRACT:
A semiconductor device formed on a semiconductor substrate and a method of forming the same. In one embodiment, the semiconductor device includes a gate over the semiconductor substrate and a dielectric liner on a sidewall of the gate. The semiconductor device also includes an extension spacer adjacent and extending laterally beyond the dielectric liner along the semiconductor substrate. The semiconductor device further includes a source/drain located below an upper surface of the semiconductor substrate and adjacent a channel region under the gate. The source/drain extends under the dielectric liner and the extension spacer. The semiconductor device still further includes a silicide region over a portion of the source/drain and extending laterally beyond the extension spacer along the semiconductor substrate. Thus, the extension spacer is interposed between the dielectric liner and the silicide region located over a portion of the source/drain.

REFERENCES:
patent: 6274446 (2001-08-01), Agnello et al.
patent: 6642119 (2003-11-01), Pelella et al.
patent: 6753574 (2004-06-01), Yamaguchi et al.
patent: 6812073 (2004-11-01), Bu et al.
patent: 2002/0081794 (2002-06-01), Ito
patent: 2002/0130378 (2002-09-01), Forbes et al.
patent: 2005/0116360 (2005-06-01), Huang et al.
Shimizu, A., et al., “Local Mechanical Stress Control (LMC): A New Technique for CMOS-Performance Enhancement,” IEDM, 2001, pp. 433-436, IEEE, Los Alamitos, CA.

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