Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-08-30
2011-08-30
Kerveros, James C (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
08010855
ABSTRACT:
A semiconductor device is capable of being coupled to first and second debuggers, the first and second debuggers being capable of debugging a program in the semiconductor device. The semiconductor device includes a first chip, and a second chip that is coupled to the first chip. The first chip includes a first processing unit that executes a first instruction group, and a first debug control unit capable of being coupled to the first debugger to control a communication with the first debugger. The second chip includes a nonvolatile memory that stores an ID code and the program including the first and second instruction groups and, the ID code stored in the nonvolatile memory being compared with an ID code inputted from the second debugger to control permission or prohibition of a connection configuration to the second debugger, a second processing unit that executes the second instruction group, and a second debug control unit capable of being coupled to the second debugger to control a communication with the second debugger. The first debug control unit controls permission or prohibition of a connection configuration to the first debugger based on whether the connection configuration to the second debugger is permitted or not.
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Japanese Office Action dated Jun. 14, 2011 with English language translation.
Kerveros James C
McGinn IP Law Group PLLC
Renesas Electronics Corporation
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