Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1997-03-19
2001-08-14
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S528000, C438S592000
Reexamination Certificate
active
06274447
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device comprising a MOS element formed by a salicide technique, in other words, a MOS element in which metal silicide layer is formed over the surfaces of the gate electrode and source/drain regions thereof, and a fabrication method thereof.
2. Field of the Invention
Electronic devices have recently followed a path towards even smaller dimensions, with the aim of creating semiconductor integrated circuits with even greater densities and more sophisticated capabilities. This reduction in dimensions has led to a situation in which there is no option but to achieve narrower widths and shallower depths of impurity diffusion layers that form the source/drain regions (source regions or drain regions) of MOS transistors. However, as the source/drain regions become shallower, the sheet resistance of these impurity diffusion layers rises so far that the channel resistances of the transistors can no longer be ignored and, as a result, the capabilities of the semiconductor integrated circuits are degraded by delays and other problems.
A self-aligned-silicide (salicide) technique is useful for countering these problems. This technique is used to convert the surfaces of the source/drain regions and the gate electrode, which consists of polycrystalline silicon, into a self-aligned silicide, as stated in, for example: LSI Hand-book, edited by The Institute of Electronics and Communication Engineers and published by Ohmsha Ltd., p. 401. Use of the salicide technique makes it possible to lower the resistance of the source/drain regions, as necessitated by even smaller dimensions.
However, it is known that the silicification reaction is suppressed and the sheet resistance increases, either because of the high-density impurities present in the gate electrode and the source/drain regions, particularly that of arsenic used in n-channel MOS transistors, or because of the smaller dimensions necessitated by the narrower widths of the source/drain regions and the gate electrode, as has been disclosed in:
(1) Robert Beyers et. al., J. Appl. Phys. 61 (11) 1987
(2) Minoru Takahashi et. al., Ext. Abs. 1993 SSDM, p. 458
A known method of counteracting this problem is to use ion implantation before the silicification, to implant arsenic ions into the surfaces of the source/drain regions and the gate electrode, which consists of polycrystalline silicon, to make the silicon non-crystalline and thus create a low-resistance silicide.
This method is disclosed in:
(1) Hitoshi Wakabayashi et. al., Technological Research Report SDM95-173 by The Institute of Electronic, Information and Communication Engineers
(2) I. Sakai et. al. Digest 1992 Symposium on VLSI Technology, p. 66
The technique described by these papers uses a method by which impurities are implanted into the source/drain regions and gate electrode of the transistor to make the semiconductor conductive and, after that impurities are activated, arsenic is implanted therein to make the surfaces of the source/drain regions and gate electrode non-crystalline, and then the silicide layer is formed.
However, according to the technique used to implant the arsenic with the objective of creating the non-crystalline surfaces, if ion implantation is used to bombard the entire surface of the semiconductor substrate with arsenic to make it non-crystalline, that arsenic could cause counter-doping with respect to the layer of diffused p-type impurity, such as boron, so that the density of the p-type impurity in the impurity layer becomes relatively low. In order to prevent this, it is necessary to use a photoresist and pattern it so that the arsenic bombards only the n-type regions. However, this method increases the number of steps and the number of photomasks used for the patterning during ion implantation, leading to an increase in wafer processing costs.
SUMMARY OF THE INVENTION
The objective of this invention is therefore to provide a semiconductor device comprising a MOS element, in which any rise in sheet resistance due to the reduced dimensions of the source/drain regions and the gate electrode is suppressed, and a method of fabricating such a device.
In accordance with one aspect of this invention, a method of fabricating a semiconductor device comprising a MOS element, the MOS element comprises: a gate electrode consisting of a conductive layer comprising at least silicon that is formed on a substrate with an insulating film therebetween; an impurity diffusion layer configuring a source region or drain region that is formed within the semiconductor substrate; and a metal silicide layer on the surfaces of the gate electrode and the impurity diffusion layer; the method of fabricating a semiconductor device comprising the steps of:
(A) forming a conductive layer comprising at least silicon on the semiconductor substrate, with an insulating film therebetween;
(B) diffusing impurities to act as donors or acceptors into the semiconductor substrate, to form an impurity diffusion layer for configuring a source region or drain region;
(C) forming a metal layer capable of creating a silicide, on at least the surfaces of the conductive layer and the impurity diffusion layer; and
(D) performing thermal processing to convert the metal layer into a silicide;
wherein the fabrication method comprises a further step of using ion implantation to implant atoms that do not function as donors or acceptors into at least the conductive layer and the impurity diffusion layer, before the step (C) of forming the metal layer.
The semiconductor device of this invention, which is produced by the fabrication method of this invention, comprises a MOS element having a gate electrode consisting of a conductive layer comprising at least silicon that is formed on a semiconductor substrate with an insulating film therebetween; an impurity diffusion layer for configuring a source region or drain region that is formed within the semiconductor substrate; and a metal silicide layer on the surfaces of the gate electrode and the impurity diffusion layer;
wherein atoms that do not function as donors or acceptors are introduced by ion implantation into the impurity diffusion layer, in addition to impurities that act as donors or acceptors.
In other words, the fabrication method of this invention uses ion implantation to implant ions of specific atoms that do not function as donors or acceptors into the surfaces of the conductive layer that configures the gate electrode of the MOS element and the impurity diffusion layers that configure the source/drain regions, before the step (C) of forming the metal layer that enables the creation of a silicide, to make the surfaces of this conductive layer and the impurity diffusion layers non-crystalline(amorphous). This step increases the reactivity of the silicon configuring these layers and thus makes it possible to perform the silicification reliably. Therefore, if the width of the gate electrode and impurity diffusion layers have become narrower as a result of the reduction in dimensions of elements, and even if the depths of these impurity diffusion layers have also become shallower, it is possible to suppress any rise in the sheet resistance of the metal silicide layers and also, since there is no counter-doping with respect to both n-type and p-type impurities, it is possible to obtain satisfactory metal silicide layers without affecting the impurity density.
In the semiconductor device and fabrication method of this invention, these atoms that do not function as donors or acceptors are at least one of noble gas selected from a group consisting of argon, krypton, neon, helium, and xenon, or at least one selected from a group consisting of silicon, germanium, carbon, and tin. Argon is even more preferable.
Since these atoms do not function as donors or acceptors, they have no effect on the density of donors or acceptors comprises within the source/drain regions. These atoms are of a suitable mass and quantity to enable efficient and reliable conversion of the si
Booth Richard
Hogan & Hartson LLP
Seiko Epson Corporation
LandOfFree
Semiconductor device comprising a MOS element and a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device comprising a MOS element and a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device comprising a MOS element and a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2476179