Semiconductor device checking method

Details Semiconductor device checking method Semiconductor device checking method

1996-05-17

1997-09-09

Chaudhari, Chandra

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

438612, 438652, H01L 2166

Patent

active

056656106

ABSTRACT:
A plated layer made of a metal which is hard to oxidize is formed on the surface of a check electrode of a semiconductor chip which is formed on a semiconductor wafer. A bump of a contactor is caused to come in contact with the check electrode on which the plated layer is formed in the direction perpendicular to the semiconductor chip. Then, a voltage is applied to the bump of the contactor to make a check such as burn-in on the semiconductor chip in a lump.

REFERENCES:
patent: 5487999 (1996-01-01), Farnworth
patent: 5508229 (1996-04-01), Baker
patent: 5585282 (1996-12-01), Wood et al.
A. Hino et al., "2-layer Flexible Printing Base, Nitto Giho", vol. 28, No. 2, pp. 57-62, Oct., 1990, with English abstract included and drawings with indications in English.

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