Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-04-20
2001-04-17
Le, Dieu-Minh T. (Department: 2184)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C326S081000
Reexamination Certificate
active
06219808
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a complementary metal oxide semiconductor (CMOS) device (broadly, complementary metal insulator semiconductor (CMIS) device), and more particularly, to the improvement of a “stuck-at-1” or “stuck-at-0” fault test function thereof.
2. Description of the Related Art
In a prior art system for testing a CMOS device, the device is driven by using a functional test pattern, and as a result, an output pattern is obtained at the outputs of the device. Then, the output pattern is compared with an expected pattern. Thus, a determination of whether or not the device is normal or abnormal is made based on whether or not the output pattern coincides with the expected pattern.
In the above-mentioned prior art system, a fault point such as a “stuck-at-1” fault point or a “stuck-at-0” fault point is estimated. Note that a “stuck-at-1” fault and a “stuck-at-0” fault will be explained later. For this purpose, special test patterns are supplied to external input terminals, thus activating a fault. Then, a plurality of test patterns are further supplied to the external input terminals, so that the activated fault propagates through the CMOS device to reach external output terminals. This will be explained later in detail.
In the above mentioned prior art system, however, when the fault is deactivated within the CMOS device before the activated fault reaches the external output terminals, a plurality of test pattern signals for activating the fault and a plurality of test pattern signals for propagating the activated fault are again supplied to the external input terminals. In addition, as the CMOS device is highly-integrated, the number of test pattern signals for activating and propagating a fault is increased. As a result, it is substantially impossible to effectively detect a fault in a highly integrated CMOS device.
On the other hand, in order to detect a fault in a CMOS device, an I
d d q
test has been adopted (see JP-A-6-118131). That is, a fault is detected by detecting an abnormal quiescent V
D D
supply current I
d d q
, i.e., a penetration current flowing within the CMOS device. In the I
d d q
test, it is unnecessary to propagate the activated fault to the external output terminals.
In the I
d d q
test, however, since it takes a long time to measure a stable I
d d q
current, it is impossible to measure all I
d d q
currents for all possible test pattern signals. Therefore, in order to decrease the I
d d q
test time, test patterns are limited to measure I
d d q
currents, or special test patterns for the I
d d q
test are used. Also, if the test pattern includes a pattern for initializing the CMOS device, it is impossible to detect a new fault. Therefore, the I
d d q
test cannot increase the rate of detection of faults.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a CMOS device capable of carrying out a complete fault detecting test at a high speed.
According to the present invention, in a semiconductor device including a high power supply line, a low power supply line, and a CMOS gate circuit having a high voltage side terminal, a low voltage side terminal and an output terminal, a first switching element is connected between the high voltage side terminal and the high power supply line, a second switching element is connected to the output terminal and the high power supply line, a third switching element is connected between the low voltage side terminal and the low power supply line, and a fourth switching element is connected to the output terminal and the low power supply line.
In a normal operation mode, the first and third switching elements are turned ON, and the second and fourth switching elements are turned OFF.
In a “stuck-at-1” fault test mode, the fourth switching element is turned ON, and the first and second switching elements are turned OFF. The third switching element can be turned ON or OFF.
In a “stuck-at-0” fault test mode, the second switching element is turned ON, and the third and fourth switching elements are turned OFF. The first switching element can be turned ON or OFF.
Also, a plurality of CMOS gate circuits are individually subjected to a “fault-at-1” fault test mode or a “fault-at-0” fault test mode, and thus, a “bridge” fault between two of the CMOS gate circuits can be detected. Note that a “bridge” fault is explained later.
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Le Dieu-Minh T.
NEC Corporation
Young & Thompson
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