Semiconductor device capable of adjusting timing of input...

Details Semiconductor device capable of adjusting timing of input... Semiconductor device capable of adjusting timing of input...

2001-02-01

2004-08-31

Dildine, R. Stephen (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S731000, C324S533000

Reexamination Certificate

active

06785858

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, a semiconductor device which can be measured while correcting signal propagation delay time in a wire on a test jig interposing between a semiconductor tester and the semiconductor device and a timing error between propagation delay time in wires.
2. Description of the Background Art
In the case of measuring electric characteristics and the like of a semiconductor device by a semiconductor tester (hereinbelow, called a tester), usually, a jig for interface (hereinbelow, called a test jig) is interposed to electrically connect the tester and the semiconductor device. Since the tester is a large and expensive facility, it is commonly used for a plurality of kinds of semiconductor devices in a semiconductor device manufacturing factory. The number of terminals and the shape of a package vary according to semiconductor devices. By replacing a test jig with another, different kinds of semiconductor devices can be measured by the same tester.
FIG. 14
is a diagram for explaining the test jig.
Referring to
FIG. 14
, a tester
200
has drivers
204
a
to
204
x
for outputting waveforms to a plurality of connection terminals, and comparators
206
a
to
206
x
for measuring waveforms of the terminals.
A test jig
202
includes a socket
212
for attaching a semiconductor device and transmission lines
208
a
to
208
x
for connecting a plurality of terminals of the socket
212
to the different connection terminals of the tester
200
. As the transmission lines
208
a
to
208
x
, for example, coaxial lines
210
are used.
FIG. 15
is a diagram showing a state where a semiconductor device is attached to the socket of the test jig.
Referring to
FIG. 15
, when the semiconductor device is attached to the socket
212
, the transmission lines
208
a
to
208
x
are electrically connected to terminals of the semiconductor device.
For example, in the case of measuring time (such as access time) between receipt of a signal from the tester and outputting of any signal by the semiconductor device, it is known that the excess time has to be subtracted from the time measured as access time. The excess time is obtained by adding the time required for a signal outputted from the tester
200
to reach the semiconductor device via the transmission lines
208
a
to
208
x
on the test jig
202
and the time required for the signal outputted from the semiconductor device to reach the tester
200
via the signal transmission lines
208
a
to
208
x.
That is, the delay time caused by the signal transmission lines
208
a
to
208
x
existing on the test jig
202
has to be especially considered and excluded. Usually, coaxial cables or wiring patterns formed on a printed wiring board are used as the transmission lines
208
a
to
208
x
. Due to the wiring length, generally, signal propagation delay time of the order of a few ns occurs.
Conventionally, a method called TDR (Time Domain Reflectmetry) which preliminarily measures the signal propagation delay time on the test jig by a tester is used. Then, another method of subtracting the preliminarily measured propagation delay time at the time of measuring electric characteristics of a semiconductor device is used.
FIG. 16
is a diagram for explaining measurement of propagation delay time by the TDR method.
FIG. 17
is a waveform chart at the time of measuring the propagation delay time by the TDR method.
Referring to
FIGS. 16 and 17
, in order to measure time T_cable of propagation of a signal through the transmission line
208
a
, a signal wave is outputted from the driver
204
a
of the tester in a state where the semiconductor device is not attached to the socket of the test jig, that is, an output end
214
of the transmission line
208
a
is open.
The signal wave outputted from the driver
204
a
passes through the transmission line
208
. The signal wave is totally reflected by the output terminal
214
which is open. The signal wave passes through the transmission line
208
a
again, and is received by the comparator
206
a
of the tester. The total time is measured by the tester. The measured time is time required for the signal wave to go and return through the transmission line
208
a
and is twice as long as the propagation time T_cable. The time which is the half of the measured time is defined as propagation delay time in the transmission line
208
a.
FIG. 18
is a diagram showing the correspondence between the transmission lines on the test jig and propagation delay time.
Referring to
FIG. 18
, propagation delay time in the transmission lines
208
a
,
208
b
,
208
c
, . . . ,
208
x
is set as T_cable-a, T_cable-b, T_cable-c, . . . , T_cable-x, respectively. Due to error factors such as variations in wiring length and mounting conditions (such as soldering) of the socket, the signal propagation delay time T_cable-a to T_cable-x in the transmission lines
208
a
to
208
x
extending from the tester to the socket varies.
FIG. 19
is a waveform chart showing a state where the waveform outputted from the tester propagates to the output end of each of the transmission lines.
Referring to
FIG. 19
, it is assumed that waveforms observed at the output ends of the transmission lines
208
a
to
208
x
are waveforms W
208
a
to W
208
x
, respectively. Propagation delay time in all the signal transmission lines
208
a
to
208
x
is measured in advance. At the time of measuring the electric characteristics of a semiconductor device or the like, measurement is performed by supplying a signal to the semiconductor device at a timing obtained by subtracting the measured propagation delay time T_cable-a to T_cable-x in the transmission lines
208
a
to
208
x.
In such a manner, although a timing error in the propagation time of Aa occurs at the ends of the socket before correction of the propagation delay time by the TDR method, the timing error can be shortened. The measured propagation delay time T_cable-a to T_cable-x is recorded as data for correction in the tester. The tester adjusts the timing of making the driver output data with reference to the correction data.
FIG. 20
is a waveform chart showing waveforms at the output ends after correction by the tester.
Referring to
FIGS. 19 and 20
, before correction of the propagation delay time by the TDR method, there is a timing error &Dgr;a in the propagation delay time between the transmission lines
208
a
to
208
x
at the ends of the socket. By performing the timing correction, the timing error &Dgr;a can be shortened to about &Dgr;b. Consequently, the correction can be made so that a semiconductor device can receive substantially (actually) simultaneously output signals at a timing, which are outputted from the tester.
In recent years, as the operating frequency increases, as seen in a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) or the like, there occurs a necessity to measure a semiconductor device which is requested to have a very small error between a data output timing reference signal and a data output timing.
The measuring accuracy has to be therefore further improved. As described above, in order to improve the accuracy of measuring a semiconductor device by a tester, it is necessary to measure the semiconductor device after accurately correcting the signal propagation delay time on the test jig, a timing error caused by variations in wiring length among the transmission lines, and the like.
Referring again to
FIG. 16
, in the method using the conventional TDR method, when the propagation delay time of, for example, the transmission line
208
a
is measured, since the timing accuracy of both the driver
204
a
and the comparator
206
a
is involved, the timing correction is limited. The timing error between the plurality of transmission lines (hereinbelow, called a skew among pins) is a value of, for example, about ±several hundreds ps. A nominal value of the value is shown under the name such as a driver skew or the li

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