Semiconductor device barrier layer

Details Semiconductor device barrier layer Semiconductor device barrier layer

2002-05-21

2004-02-03

Clark, Jasmine (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S750000, C257S758000, C257S774000

Reexamination Certificate

active

06686662

ABSTRACT:

This invention relates to the fabrication of semiconductor devices and, more specifically, to barrier layers used in the metallization of semiconductor device components, and passivation of dielectric materials.
BACKGROUND OF THE INVENTION
Thin films serve a variety of different functions in the manufacture of semiconductor devices. For example, thin films are used in the construction of interconnect structures. Interconnect structures are those structures on an integrated circuit device that connect different levels of a multi-level semiconductor device, and include features such as trenches and vias in which a conductive metal is deposited. Thin films are often used to form barrier layers within a feature between a dielectric material and a conductive metal.
A typical interconnect structure is shown in FIG.
1
. An interconnect structure
11
includes an upper metallization layer
12
and lower metallization layer
13
separated by a dielectric layer
14
or insulating layer. The conductive metal layers
12
and
13
comprise metal lines
15
spaced apart within a dielectric material
16
. Conductive metal-filled vias
17
interconnect the metal lines
15
of the upper metallization layer
12
to the conductive lines
15
of the lower metallization layer
13
. Typically, in a multi-level structure, the lower metallization layer
13
is fabricated using a process known as single damascene, and the dielectric layers
14
and upper metal layers
12
are fabricated using a process known as dual damascene. These damascene processes are known to those skilled in the art.
In either damascene process, a feature, such as a trench, via or combination thereof, is etched in the dielectric material
16
. A barrier layer
18
is then deposited in the feature using a known process such as sputter deposition. The barrier layer
18
forms a thin film conforming to the sidewalls and bottom of the feature. A seed layer
19
is then deposited over the barrier layer
18
, and the conductive metal is electroplated in the feature over the seed layer
19
. The device is planarized after these deposition steps to remove excess film and metal outside the feature. The barrier layer
18
prevents the diffusion of the conductive metal into the dielectric material, and the seed layer
19
promotes adherence of the conductive metal to the barrier layer
18
. Refractory metals and/or refractory metal alloys are often used in fabrication of barrier layers. For example tantalum (Ta) and/or tantalum nitride (TaN) may be applied as a component of a barrier layer.
However, Ta is polycrystalline and diffusion of copper through the Ta grain boundaries persists. Previous attempts to solve this problem included increasing the thickness of the Ta film, adding nitrogen to the Ta to block grain boundary diffusion paths, or use a Ta/TaN dual barrier layer. Unfortunately, these options increase the resistance of the barrier layer, which adversely impacts electromigration. This is especially the case where the barrier layer
18
is deposited on the bottom of a via over the lower metallization layer
13
and line
15
, as shown in
FIG. 1
; thereby increasing the resistance across the interconnect structure.
In addition, the Ta film does not prevent water adsorbed in the porous low-k dielectric materials from attacking the copper. Low-k dielectric materials are used in part because of their low resistivity, and include those dielectric materials having a dielectric constant less than about 4.0. Organisilicates are the most commonly used low-k dielectrics. However, low-k dielectrics are very porous, and are hygroscopic. Water captured within the porous low-k dielectric will evaporate. Water vapor can migrate to the copper, oxidizing the metal. Moreover, Ta adheres poorly to the organosilicates and other spin on low-k dielectric materials used in the fabrication of interconnect structures.
SUMMARY OF THE INVENTION
The present invention is for a barrier layer, and process for fabricating a barrier layer, that utilizes a novel dual film. The two films comprising the barrier layer are formed within a recess or feature such as a trench, via, hole etc., formed in a device topographical structure. The barrier layer includes a first film comprising silicon nitride (SiN), which is disposed along a surface of a dielectric material within the device feature. A second film, or refractory metal film, is deposited along the sidewalls and bottom of the feature and over the silicon nitride film. The term refractory metals as used in this disclosure shall also include refractory metal alloys. A metal seed layer is then deposited over the barrier layer, and the conductive metal is then deposited within the feature over the seed layer.
The present invention is described in the context of fabrication of an interconnect structure, but it is not intended to be so limited, but may be applied to any device component requiring a barrier layer for metallization and/or dielectric passivation. An interconnect structure generally includes a plurality of layers (dielectric layers) of dielectric materials deposited atop one another. These dielectric layers are separated by etch stop layers, which, in part, define boundaries of features to be etched in the dielectric materials. The dielectric materials may include low-k dielectric materials, which term as used in this disclosure include spin-on dielectrics such as organosilicates, having a dielectric constant of up to about 4.0.
A recess or feature, such as a via or trench, etched in the dielectric material has at least one or more, sidewalls, which may include one or more exposed surfaces of the dielectric material. The surface of the dielectric is exposed to nitrogen at a predetermined temperature and pressure for a timed duration. The surface of the dielectric undergoes nitridation, which forms a Si
3
N
4
film along the dielectric surface. The nitridation alters the chemical composition of a portion of the dielectric, forming a film integrated within the dielectric material and along the dielectric surface.
The refractory metal film is then deposited within the feature conforming to the sidewalls and bottom of the feature and over the silicon nitride film. A metal seed layer is deposited over the refractory metal film. The conductive metal is then deposited within the feature, and the device is planarized using chemical mechanical planarization (“CMP”) to remove excess metal and films outside the device feature.
In this manner, the Si
3
N
4
film (or first film) seals the surfaces of the dielectric material, and in combination with the refractory metal film, serves as a barrier layer to inhibit diffusion of the conductive metal to the dielectric. The Si
3
N
4
also promotes adherence of the refractory metal to the surface of the low-k dielectric.


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