Electronic digital logic circuitry – With test facilitating feature
Reexamination Certificate
2001-10-09
2003-05-13
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
With test facilitating feature
C326S009000, C326S014000
Reexamination Certificate
active
06563335
ABSTRACT:
Japanese Patent Application No. 2000-317496, filed on Oct. 18, 2000, is hereby incorporated by reference in its entirety.
TECHNICAL FIELD
The present invention relates to a semiconductor device and a test method therefor, and, more particularly, to a semiconductor device and a test method therefor which are suitable for an application specific integrated circuit including a circuit designed by a user.
BACKGROUND
Development on application specific integrated circuits (ASICs) is carried out by using development tools, which have been built by a chip maker, with basic cells prepared by the chip maker as structural units to achieve specifications peculiar to a user. As such ASICs can significantly contribute to reducing the number of components of a user product, demands for ASICs are increasing.
In developing an ASIC, a user makes logic design that achieves, for example, desired functions, provides a chip maker with designed circuit diagrams and a test pattern for verifying whether the functions are as designed or not and asks the chip maker to make a layout design, execute mask fabrication and so forth. Alternatively, the user completes a process up to making of the layout design, provides the chip maker with layout data that has been verified to operate with specified AC characteristics by development tools or the like and a test pattern and asks the chip maker to execute mask fabrication and so forth.
An ASIC developed in this manner is normally provided with a test circuit which allows a chip maker to determine if the ASIC passes. After manufacturing chips using fabricated masks, the chip maker sorts out defective chips by checking if the chips pass or fail using the test pattern provided by the user and through a test conducted by the test circuit.
SUMMARY
One aspect of the present invention relates to a semiconductor device including a test cell for performing delay evaluation of a signal input from a first I/O circuit and output to a second I/O circuit, the semiconductor device comprising:
first to N-th delay paths for respectively delaying a signal input from the first I/O circuit by first to N-th delay values different from one another and for outputting the delayed signal to the second I/O circuit; and
a delay path switching circuit that selects one of the first to N-th delay paths through which a signal input from the first I/O circuit is output to the second I/O circuit.
Another aspect of the present invention relates to a test method for a semiconductor device including first and second I/O circuits and first to N-th delay paths, which are provided between the first and second I/O circuits, for respectively delaying a signal by first to N-th delay values different from one another, the method comprising steps of:
measuring first to N-th delay times between a signal input from the first I/O circuit and a signal output to the second I/O circuit being output via each of the first to N-th delay paths corresponding to the input signal for each of the first to N-th delay paths; and
testing the semiconductor device based on a difference between at least two of the first to N-th delay times.
REFERENCES:
patent: 5578938 (1996-11-01), Kazami
patent: 6239611 (2001-05-01), Matera
Seiko Epson Corporation
Tran Anh Q
LandOfFree
Semiconductor device and test method therefor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and test method therefor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and test method therefor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3084366