Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2000-04-27
2001-09-04
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S698000, C257S692000
Reexamination Certificate
active
06285086
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a substrate for a semiconductor device and a semiconductor device, and more particularly, to a substrate for a semiconductor device and a semiconductor device substantially reduced to a chip size suitable for high density packaging.
2. Description of the Background Art
Chip-size Package (CSP) semiconductor devices such as QFP (Quad Flat Package) type or BGA (Ball Grid Array) type devices have been in wide use to cope with the recent trend toward lighter and more compact apparatus in the market of electrical appliances and adapt to automated assembly process. Increased speed and number of functions in signal processing by semiconductor elements incorporated in these semiconductor devices require a larger number of external connection terminals.
In such a case, a BGA type device having external connection terminals arranged two-dimensionally at the bottom of the semiconductor device is employed. Some devices are formed to be as small as possible so that they can be incorporated into compact mobile equipment, in other words they are formed to have a size close to a chip size. There is a conventional resin encapsulation type semiconductor device as disclosed in Japanese Patent Laying-Open No. 9-121002. In such devices, a semiconductor chip is mounted on an interconnection substrate, electrical conduction with the interconnection substrate is secured by wire-bonding, and then resin encapsulation is achieved to protect the semiconductor chip, wiring and the like. External connection terminals are formed by reflow or the like.
A semiconductor device having this structure is mounted by reflow onto a wiling board such as a printed circuit board for an actual electronic device. When these external connection terminals are formed or when the semiconductor device is mounted onto the wiring board by reflow, moisture in the semiconductor device could evaporate and expand. In order to solve the problem, as shown in
FIG. 7
, a plan view of a conventional semiconductor device from the surface to form an external connection terminal, a second through hole
19
to discharge moisture remaining between the semiconductor chip of the semiconductor device and an insulating substrate
15
is provided in insulating substrate
15
in a region between a plurality of first through holes
18
where external connection terminals are formed. Note that a land
17
for connecting an external connection terminal is exposed from first through hole
18
.
After the mounting by reflow, stress is generated at the connection portion between the semiconductor device and the wiring board because of their different line expansion coefficients or the like in a heating cycle or the like. The above-described semiconductor device has one side of semiconductor chip
1
encapsulated with mold resin
2
, and therefore a bowing part forms in the semiconductor device as shown in
FIG. 6
, if the temperature changes because of a phenomenon characteristic to a bimetal-like structure between semiconductor chip
1
and mold resin
2
.
FIG. 6
is a view showing stress caused between mounting board
10
and the semiconductor device. The semiconductor device is mounted to mounting board
10
by an external connection terminal
4
.
The difference in the above line expansion coefficient or the bowing of the semiconductor device could cause cracks at the connection portion between the semiconductor device and the wiring board, leading to breaking in some cases. At this time, if there are small holes (second through holes) to prevent the trouble associated with reflow as described above, the circular shape of the small holes could not provide enough stress alleviation effect, and therefore a trouble could be caused in a heating cycle following the mounting. Such conventional small holes are formed by drilling and therefore have a circular shape.
SUMMARY OF THE INVENTION
It is an object of the present invention is to provide a semiconductor substrate for a semiconductor device and a semiconductor device which allow the reliability relative to thermal stress to be improved after being mounted onto a wiring board such as a printed circuit board in a chip-size package.
A substrate for a semiconductor device according to one aspect of the present invention includes an insulating substrate and a conductive layer. The insulating substrate has one surface, the other surface opposing the one surface, and a plurality of first through holes communicating between the one surface and the other surface. The conductive layer has a conductive portion formed to cover the openings of the first through holes in the one surface of the insulating substrate. In a region of the insulating substrate without the conductive layer, a second through hole communicating between the one surface and the other surface is formed. The shape of the opening of the second through hole has a corner portion.
Preferably, the shape of the opening of the second through hole is a cross shape. Also preferably, the shape of the opening of the second through hole is an L shape. The shape of the opening of the second through hole may be a rectangular shape.
The second through hole is preferably provided between a plurality of the first through holes. The second through hole may be provided outside the region of the insulating substrate where the conductive portion is formed. The insulating substrate has a region without the conductive portion in the center, and the second through hole may be provided in this central region.
A semiconductor device according to another aspect of the present invention includes an insulating substrate, a conductive layer and a semiconductor chip. The insulating substrate has one surface, the other surface opposing the one surface, and a plurality of first through holes communicating between the one surface and the other surface. The conductive layer has a conductive portion formed to cover the openings of the first through holes in the one surface of the insulating substrate. The semiconductor chip is mounted on the one surface of the insulating substrate. A second through hole communicating between the one surface and the other surface is formed in the region of the insulating substrate without the conductive layer. The shape of the opening of the second through hole has a corner portion. The conductive layer and the semiconductor chip are electrically connected.
Preferably, the semiconductor device further includes a plurality of external connection terminals electrically connected to the conductive portion through the first through holes in the insulating substrate. Also preferably, the semiconductor device further includes a bonding wire to electrically connect the conductive layer and the semiconductor chip.
Preferably, the shape of the opening of the second through hole is a cross shape. Also preferably, the shape of the opening of the second through hole is an L shape. The shape of the second through hole may be a rectangular shape.
Preferably, the second through hole is provided between a plurality of the first through holes. The second through hole may be provided outside the region of the insulating substrate where the conductive portion is formed. The insulating substrate has a region without the conductive portion in the center and the second through hole may be formed in this central region.
According to the present invention, the shape of a small hole (second through hole) provided in a region without a conductive portion as a land for an external connection terminal in order to prevent the trouble associated with heat at the time of packaging is not circular, and has a shape easy to deform by stress caused by the heat. Since the small hole deforms, the binding force generated between terminals upon the substrate deformation after packaging is reduced, which alleviates stress imposed upon the terminals, so that the semiconductor device can resist thermal stress after the semiconductor device is mounted onto a mounting or wiring board.
The use of
Juso Hiroyuki
Sota Yoshiki
Clark Sheila V.
Nixon & Vanderhye
Sharp Kabushiki Kaisha
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