Semiconductor device and method of manufacturing the same

Details Semiconductor device and method of manufacturing the same Semiconductor device and method of manufacturing the same

2006-08-10

2009-06-30

Lebentritt, Michael S (Department: 2829)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S296000, C438S564000, C438S569000, C438S578000, C438S632000, C257SE21012, C257SE21016, C257SE21274, C257SE21576, C257SE21578

Reexamination Certificate

active

07553748

ABSTRACT:
According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to form a semiconductor device. A spacer is formed on a surface of the gate structure. An insulating interlayer pattern is formed on the substrate including the gate structure, and an opening is formed through the insulating interlayer pattern corresponding to an impurity region of the substrate. A conductive pattern is formed in the opening and a top surface thereof is higher than a top surface of the insulating interlayer pattern. Thus, an upper portion of the conductive pattern is protruded from the insulating interlayer pattern. A capping pattern is formed on the insulating interlayer pattern, and a sidewall of the protruded portion of the conductive pattern is covered with the capping pattern. Accordingly, the capping pattern compensates for a thickness reduction of the gate mask.

REFERENCES:
patent: 6171954 (2001-01-01), Hsu
patent: 2002/0163082 (2002-11-01), Lee et al.
patent: 2002/0185662 (2002-12-01), Watatani
patent: 2005/0014338 (2005-01-01), Kim et al.
patent: 10-233451 (1998-09-01), None
patent: 11-177089 (1999-07-01), None
English language abstract of Korean Publication No. 10-233451.
English language abstract of Japanese Publication No. 11-177089.

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