Semiconductor device and method of manufacturing the same

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics

Reexamination Certificate

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Details

C257S301000, C257S306000, C257S310000, C257S774000, C257SE29029, C257SE21661, C257SE27016, C257SE27098, C439S395000

Reexamination Certificate

active

07417302

ABSTRACT:
In a method of manufacturing a semiconductor device, a first insulation layer on the substrate is patterned to form a first opening having a first width. A lower electrode is formed along an inner contour of the first opening. A second insulation layer on the first insulation layer is patterned to form a second opening that has a second width greater than the first width and is connected to the first opening with a stepped portion. A dielectric layer is formed on the lower electrode in the first opening, a sidewall of the second opening and a first stepped portion between the first insulation layer and the second insulation layer, so that the electrode layer is covered with the dielectric layer. An upper electrode is formed on the dielectric layer. Accordingly, a leakage current between the lower and upper electrodes is suppressed.

REFERENCES:
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patent: 6320244 (2001-11-01), Alers et al.
patent: 6346454 (2002-02-01), Sung et al.
patent: 6391707 (2002-05-01), Dirnecker et al.
patent: 6452251 (2002-09-01), Bernstein et al.
patent: 6617208 (2003-09-01), Saran
patent: 7220652 (2007-05-01), Kim et al.
patent: 2006/0289999 (2006-12-01), Lee et al.
patent: 2003-0077284 (2003-10-01), None
patent: 1020040004809 (2004-01-01), None

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