Semiconductor device and method of manufacturing the same

Details Semiconductor device and method of manufacturing the same Semiconductor device and method of manufacturing the same

2007-12-04

2007-12-04

Chen, Jack (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S269000

Reexamination Certificate

active

11485895

ABSTRACT:
Provided are a semiconductor device and a method of manufacturing the same. The method includes the steps of: forming a first silicon layer on a semiconductor substrate; patterning the first silicon layer formed on the semiconductor substrate, and exposing a channel region; forming a second silicon layer on the semiconductor substrate in which the channel region is exposed; removing the first silicon layer, and forming source and drain regions; and forming a third silicon layer in the source and drain regions. According to the manufacturing method, it is possible to minimize defects in a silicon interface by forming the source and drain using only a selective epitaxial growth method without a dry-etching process. Also, since stress is concentrated to a silicon channel region, hole mobility and driving current characteristics are considerably improved.

REFERENCES:
patent: 6281062 (2001-08-01), Sanchez
patent: 6707062 (2004-03-01), Lee
patent: 6762463 (2004-07-01), Kim
patent: 6872625 (2005-03-01), Schmidt et al.
patent: 6887762 (2005-05-01), Murthy et al.
patent: 6937516 (2005-08-01), Fazan et al.
patent: 6946350 (2005-09-01), Lindert et al.
patent: 7211491 (2007-05-01), Cho
patent: 7211871 (2007-05-01), Cho
patent: 97-470 (1995-04-01), None
‘35% Drive Current Improvement from Recessed-SiGe Drain Extensions on 37 nm Gate Length PMOS’ Chidambaram et al., 2004 Symposium on VLSI Technology Digest of Technical Papers, pp. 48-49.
‘Lattice strain analysis of transistor structures with silicon-germanium and silicon-carbon source/drain stressors’ Ang et al., Applied Physics Letters 86, 093102, 2005 American Institute of Physics.
‘A Systematic Study of Trade-offs in Engineering a Locally Strained pMOSFET’ Nouri et al., Applied Materials, Sunnydale, CA 2004. IEEE.
‘A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors’ Ghani et al., Portland Technology Development, Hillsboro, OR, 2003.

Affiliated with

Also associated with

Rating

Semiconductor device and method of manufacturing the same does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device and method of manufacturing the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method of manufacturing the same will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3870314