Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-08-31
2004-01-27
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S344000, C257S346000
Reexamination Certificate
active
06683349
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing it, and more particularly to technology of a high withstand voltage MOS transistor that is applied to e.g. an IC for driving liquid crystal.
2. Description of the Related Art
Now referring to the drawings, an explanation will be given of a conventional semiconductor device and a method of manufacturing it.
As a high withstand voltage element applied to the IC for driving liquid crystal, e.g. an LD (Lateral Double diffused) MOS transistor structure has been proposed. This DMOS transistor structure refers to an element in which impurities of a different conduction type are diffused into a diffused layer previously formed on the surface side of a semiconductor substrate to form new diffused layers and a difference of diffusion in the lateral direction between the diffused layers is used as an effective channel length. It forms a short channel and hence is suited to realize a low ON-resistance.
FIG. 7
is a sectional view for explaining a conventional DMOS transistor illustrated in an N-channel type DMOS transistor structure. Although no explanation will be given of a P-channel type DMOS transistor structure, as well known, it can have the same structure as the N-channel type DMOS transistor structure.
In
FIG. 7
, reference numeral
51
denotes a semiconductor substrate of one conduction type, e.g. P type. Reference numeral
52
denotes an N type well within which a P type body layer
53
is formed. An N type diffused layer
54
is formed within the P type body layer
53
. An N type diffused layer
55
is formed within the N type well
52
. A gate electrode
57
is formed on a substrate surface through a gate oxide film
56
. A channel layer
58
is formed in the surface layer of the P type body layer
53
immediately below the gate electrode
57
.
The N type diffused layer
54
serves as a source diffused layer, the N type diffused layer
55
serves as a drain diffused layer and the N type well
52
below a LOCOS oxide film
59
serves as a drift layer. Reference numerals
60
and
61
denote a source electrode and a drain electrode, respectively. Reference numeral
62
denotes a P type diffused layer for taking the potential of the P type body layer
53
. Reference numeral
63
denotes an interlayer insulating film.
An explanation will be given of a method of manufacturing the above DMOS transistor structure. N type impurities are ion-implanted into the semiconductor substrate
51
to form the N type well
52
. After the gate oxide film
56
has been formed on the substrate
51
, the gate electrode
57
is formed through the gate oxide film
56
. Using the gate electrode
57
as a mask, the P type impurities are ion-implanted and diffused to form the P type body layer
53
. Thereafter, the N type diffused layers
54
and
55
are formed.
In the DMOS transistor described above, since the N type well
52
is formed by diffusion, the dopant density on the surface of the N type well
52
becomes high, thereby facilitating a current flow on the surface of the N type well
52
and realizing high withstand voltage.
The DMOS transistor having the structure described above is referred to as a relaxing-surface type (Reduced SURface Field:RESURF) DMOS in which the dopant density of the drift layer of the N type well
52
is set so as to satisfy the RESURF requirement. Such technology is disclosed in JP-A-9-139438.
In the above DMOS transistor structure, as seen from
FIG. 7
, the N type well
52
is uniformly formed to have the same depth. This was an obstacle against realization of a higher withstand voltage and further reduction of the ON resistance.
Further, since the P type body layer
53
is formed to surround the entire N-type diffused layer
54
, there is a problem that the junction capacitance at this region is disadvantageously increased.
SUMMARY OF THE INVENTION
A first object of the invention is to provide a semiconductor device with endurance to a high voltage and reduced ON resistance.
A second object of the invention is to provide a method of manufacturing such a semiconductor device.
In order to attain the above object, the semiconductor device according to the invention includes a gate electrode on a P type well through a gate oxide film, a heavily-doped N type source layer formed so as to be adjacent to the one end of the gate electrode, an N type drain layer formed apart from the other end of the gate electrode, a P type body layer below the gate electrode, and a lightly-doped drain layer formed in an area extending from below the gate electrode to the heavily-doped N type drain layer so that it is shallow at least below the gate electrode and deep in the vicinity of the heavily-doped N type drain layer.
The semiconductor device according to the invention is manufactured as follows.
First, two kinds of N type impurities are ion-implanted into a P type well to form an N type lightly doped drain layer in a later step. Thereafter, a certain region on the P type well is selectively oxidized to form a local oxidation film and to form lightly-doped N type layers at a relatively shallow or surface position and a relatively deep position in the P type well, respectively on the basis of a difference in a diffusion coefficient between the two kinds of N type impurities. Using a resist film formed on the P type well on a region where a drain is to be formed, P type impurities are ion-implanted in the P type well of a region where a source is to be formed, and thereafter diffused so that the N type layer formed at the deep position in the P type well of the region where the source is to be formed is canceled by the diffused P type impurities, thereby forming a lightly-doped N type drain layer which comprises a first N type layer formed at a shallower position and a second N type layer formed at a deep position. N type impurities are ion-implanted in the P type well to form a heavily-doped source layer so as to be adjacent to the one end of a gate electrode to be formed in a later step and a heavily-doped N type drain layer at a position apart from the other end of the gate electrode. Further, P type impurities are ion-implanted in the P type well to form a P type body layer from below the one end of the gate electrode so as to be adjacent to the N type source layer. Finally, the gate electrode is formed on the gate oxide film which is formed on the N type well.
REFERENCES:
patent: 5780912 (1998-07-01), Burr et al.
patent: 5874768 (1999-02-01), Yamaguchi et al.
patent: 6087232 (2000-07-01), Kim et al.
patent: 6215152 (2001-04-01), Hebert
patent: 6242787 (2001-06-01), Nakayama et al.
patent: 2062349 (1981-05-01), None
patent: 2000312002 (2000-11-01), None
Aoyama Masashige
Arai Takashi
Taniguchi Toshimitsu
Fish & Richardson P.C.
Lee Eddie
Nguyen Joseph
Sanyo Electric Co,. Ltd.
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