Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-11-13
2003-11-18
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S187000, C438S305000, C438S232000, C438S527000, C438S595000, C438S766000, C438S926000
Reexamination Certificate
active
06649462
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-223392, filed Jul. 24, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device that comprises a semiconductor substrate and an insulated gate field-effect transistor (MISFET) provided on the substrate, and to a method of manufacturing the semiconductor device. The invention relates to the gate electrode of a MISFET, which is made of metal, and to a method of manufacturing the gate electrode.
2. Description of the Related Art
In a method of manufacturing a MOSFET whose gate electrode is made of metal, the metal gate is formed by damascene metal-gate process. In the damascene metal-gate process, the trench made by removing a dummy gate is filled with metal. The smaller and narrower the metal gate of the MOSFET, the more difficult it is to fill the trench with metal. Therefore, there is a demand for a MOSFET structure and a method, with which damascene metal-gate process can be successfully performed even if the metal gate is small and narrow.
FIGS. 1A and 1B
are sectional views, explaining damascene metal-gate process of forming the gate electrode of a conventional MOSFET.
In this damascene metal-gate process, a dummy gate (not shown) is removed, making a trench
90
in an inter-layer insulating film
95
as shown in FIG.
1
A. Thereafter, as
FIG. 1B
shows, metal
96
is deposited on the film
95
and in the trench
90
. In
FIGS. 1A and 1B
, numeral
91
designates a dummy-gate insulating film, numeral
92
indicates a silicon nitride film that surrounds the trench
90
, numeral
93
denotes a gate side-wall (silicon oxide film), numeral
94
represents a silicon nitride film, and numeral
97
denotes a gate insulating film.
The MOSFET is so small that its channel length is, for example, 30 nm and the trench
90
has a height of, for example, 220 nm, as is illustrated in
FIGS. 1A and 1B
. The trench
90
therefore has a very large aspect ratio. Due to the large aspect ratio, the trench
90
cannot be completely filled with metal
96
if the metal
96
is deposited by sputtering. Consequently, a space S is made in the trench
90
.
To fill the trench
90
with metal
96
fully and completely, the height of the dummy gate may be decreased. However, the height of the dummy gate cannot be easily reduced, because it is also used the dummy gate as a polishing stopper of the inter-layer insulating film
95
by chemical mechanical polishing (CMP).
If the trench
90
is made narrower so that it may be filled with metal
96
completely, the metal
96
will form a metal gate that has but a small cross section. The metal gate inevitably has an excessively high resistance, jeopardizing the high performance of the MOSFET. The trench
90
may be broadened. If the trench
90
is broadened, however, the MOSFET will have a long gate length, which also impairs the performance of the MOSFET.
As described above, the conventional damascene metal-gate process is disadvantageous because it is difficult to fill up a trench with metal to form the metal gate of a MOSFET particularly when the metal gate is small and narrow. If the trench is made shallow so as to be completely filled with metal, the resultant meal gate will have a high resistance, jeopardizing the high performance of the MOSFET. If the trench is broadened for the same objective, the gate length will increase, inevitably impairing the performance of the MOSFET.
BRIEF SUMMARY OF THE INVENTION
According to one aspect of the present invention, there is provided a semiconductor device semiconductor device which comprises: a semiconductor substrate; at least one pair of impurity-diffused layers formed in a surface of the semiconductor substrate, isolated from each other and constituting a drain region and a source region of an insulated gate field-effect transistor; a channel region provided between the drain region and the source region; a gate insulating film provided on the channel region; a gate electrode including a lower part and an upper part, the lower part having a lower surface and sides, the upper part having a lower surface, the lower surface of the lower part contacting the gate insulating film, and the upper part being longer than the lower part in a lengthwise direction of the gate electrode; and a first insulating film interposed between the lower surface of the upper part of the gate electrode and the semiconductor substrate, surrounding at least the sides of the lower part of the gate electrode, which face the drain and source regions, and having parts located adjacent to the sides of the lower part of the gate electrode and having a height greater than a thickness of the other parts located between the lower surface of the upper part of the gate electrode and the semiconductor substrate.
According to another aspect of the invention, there is provided a method of manufacturing a semiconductor device, the method comprises: preparing a semiconductor substrate; forming a dummy-gate insulating film and a dummy gate having a circumferential surface, on a region of the semiconductor substrate, in which an insulated gate field-effect transistor will be formed; introducing an impurity into a surface of the semiconductor substrate selectively, thereby forming a drain region and a source region of the insulated gate field-effect transistor and forming a channel region between the drain region and the source region; forming a first insulating film on the circumferential surface of the dummy gate, the first insulating film having a predetermined etching ratio to the dummy gate; forming a second insulating film above the semiconductor substrate, the second insulating film having a predetermined etching ratio to the first insulating film; processing the second insulating film, thereby giving a substantially flat surface thereto and burying the dummy gate and the first insulating film in the second insulating film; removing a part of the first insulating film to leave the remaining part of the first insulating film at a prescribed height, the remaining part contacting the circumferential surface of the dummy gate; removing the dummy gate and the dummy-gate insulating film above the channel region, thereby making a trench surrounded by the second insulating film and the first insulating film; forming a gate insulating film on the channel region; and filling the trench with metal, thereby forming a gate electrode.
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Matsuda et al.; “Performance Improvement of Metal Gate CMOS Technologies”; Symposium on VLSI Technology Digest of Technical Papers, pp. 63-64, 2001.
Yagishita et al.; “High Performance Metal Gate MOSFETs Fabricated by CMP For 0.1 &mgr;m Regime”; IEDM Technical Digest, pp. 785-788, 1998.
Chatterjee et al.; “Sub-100nm Gate Length Metal Gate NMOS Transistors Fabricated by a Replacement Gate Process”; IEDM Technical Digest, pp. 821-824, 1997.
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Azuma Atsushi
Matsuda Satoshi
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Pompey Ron
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