Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-11-02
2003-11-04
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S267000
Reexamination Certificate
active
06642103
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a semiconductor device comprising a semiconductor body which is provided at a surface with a non-volatile memory cell.
BACKGROUND OF THE INVENTION
Such a semiconductor device is known from U.S. Pat. No. 5,607,871. In the known semiconductor device, to non-volatile memory cell comprises a source and a drain, and an access gate which is electrically isolated from a gate structure comprising a control gate. The gate structure is electrically insulated from the semiconductor body by a gate dielectric which is provided with a floating gate acting as a charge-storage region wherein data in e form of electric charge can be stored. The access gate has a substantially flat surface portion extending substantially parallel to the surface of the semiconductor body. The access gate is provided by a patterned polysilicon layer which overlaps the gate structure as well as an adjacent gate structure and stretches out to substantially beyond the outermost side walls of the gate structures. In between the gate structures, the patterned polysilicon layer is disposed above the drain, which is locally provided in the semiconductor body. The source is provided in the semiconductor body, while being aligned to the patterned polysilicon layer.
A disadvantage of the known semiconductor device is that, owing to the large topography at the location of the gate structures and, hence, of a polysilicon layer applied on top of these gate structures, photolithographic patterning of the polysilicon layer is difficult. When a photoresist layer formed on top of the polysilicon layer is exposed to light so as to form a resist pattern, the exposed light is reflected in oblique directions on the surface of the polysilicon layer. As a consequence, the resist pattern is deformed, resulting in a poor dimensional accuracy of the patterned polysilicon layer. As the patterned polysilicon layer is disposed above the drain, other disadvantages of the known semiconductor device are that the source and the drain cannot be formed in a single step and that cross-talk takes place between the patterned polysilicon layer and the drain during operation of the memory cell.
The above-described non-volatile memory cell comprises an access transistor and a floating gate transistor, which floating gate transistor comprises a floating gate whereon data in the form of electric charge can be stored. As is well known to those skilled in the art, a so-called charge trapping transistor can be used instead of the above-mentioned floating gate transistor. Such a charge trapping transistor comprises a control gate which is electrically insulated from the semiconductor body by a gate dielectric, which gate dielectric comprises a distribution of mutually separated trapping centers wherein electric charge can be stored. In such a charge trapping transistor, electric charge cannot only be provided throughout the length of the channel but also only on the source side of the channel or only on the drain side of the channel. Since these different conditions can be distinguished in the reading process, it is possible to store two bits per memory cell.
Whether a floating gate is used for charge storage, as is the case in the known semiconductor device, or a gate dielectric comprising mutually separated trapping centers makes no difference with regard to the above-mentioned disadvantages. These disadvantages also occur in a semiconductor device with a charge trapping transistor.
SUMMARY OF THE INVENTION
The invention has for its object inter alia to provide a semiconductor device with a non-volatile memory cell, which memory cell can be manufactured more easily and more accurately, and which enables the earlier-mentioned problem of cross-talk during operation to be counteracted.
The semiconductor device in accordance with the invention comprises a semiconductor body which is provided at a surface with a non-volatile memory cell comprising a source and a drain, and an access gate which is electrically insulated from a gate structure comprising a control gate, the gate structure being electrically insulated from the semiconductor body by a gate dielectric, which is provided with a charge-storage region wherein data in the form of electric charge can be stored, and the access gate having a substantially flat surface portion extending substantially parallel to the surface of the semiconductor body and having the shape of a block which is disposed against the gate structure without overlapping the gate structure. When the access gate is formed by means of photolithographic patterning of a conductive layer, light, which is emitted to pattern an overlying photoresist layer, will not be reflected in oblique directions on the surface of the conductive layer. Hence, the access gate can be formed with a larger dimensional accuracy. Furthermore, the source and the drain can be formed in a single step by using the gate structure together with the access gate as a mask. In this way, cross-talk between the drain and (the conductive layer providing) the access gate can be counteracted.
The charge-storage region may be formed, for example, by a floating gate. In another embodiment, the charge-storage region comprises a distribution of mutually separated trapping centers. The gate dielectric provided with the distribution of mutually separated trapping centers may, for example, be a silicon oxide layer with contaminations, for example metal particles, distributed therein, the contaminations providing the trapping centers. However, a more widespread way is the use of a gate dielectric comprising a double layer of two different materials which form a border layer supplying the mutually separated trapping centers. In order to increase the compatibility with standard CMOS processing, the double layer is advantageously formed by a layer of silicon oxide and an adjacent layer of silicon nitride.
In a further embodiment of the semiconductor device in accordance with the invention, the substantially flat surface portion of the access gate is located at substantially the same height as the top surface portion of the gate structure. In this way, the combined structure of gate structure and access gate is substantially flat.
If the non-volatile memory cell comprises one access gate, which memory cell is also referred to as two-transistor (2T) cell, the access gate is advantageously provided at the side of the gate structure adjacent to the source. If an access transistor is provided at the side of the source, the programming voltage necessary for switching is lower than the programming voltage necessary for switching when the access transistor is provided at the side of the drain, so that the former access transistor can be processed with a thinner gate dielectric.
Further advantageous embodiments of the semiconductor device in accordance with the invention are described in the dependent claims.
The invention further relates to a method of manufacturing a semiconductor device comprising a semiconductor body which is provided at a surface with a non-volatile memory cell.
Such a method is known from U.S. Pat. No. 5,607,871. In the known method, the semiconductor body is provided with a drain in between a gate structure and an adjacent gate structure, prior to the application of a conductive layer, i.e. a polysilicon layer. The polysilicon layer is subsequently patterned in such a way that it overlaps the gate structure as well as the adjacent gate structure and stretches out to substantially beyond the outermost side walls of these gate structures. After patterning of the polysilicon layer, the semiconductor body is provided with a source, which is aligned to the patterned polysilicon layer.
A disadvantage of this method is that, owing to the large topography at the location of the gate structures and, hence, of the polysilicon layer applied on top of these gate structures, photolithographic patterning of the polysilicon layer is difficult. When a photoresist layer formed on top of the polysilicon layer is exposed to light so as to for
Slotboom Michiel
Widdershoven Franciscus Petrus
Wils Nicole Anne Helena Freddy
Nhu David
Waxler Aaron
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