Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-07-23
2003-02-04
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S627000, C438S633000, C438S634000, C438S636000, C438S637000, C438S638000, C438S687000, C257S750000, C257S751000, C257S760000, C257S762000
Reexamination Certificate
active
06514852
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a method for manufacturing semiconductor devices, and more particularly to a semiconductor device manufacturing method which addresses the need for further miniaturization of interconnection patterns.
(b) Description of the Prior Art
In response to an increasing need for further miniaturization and integration of semiconductor devices, formation of an embedded interconnection structure by using a dual damascene technique is now attracting attention. Also, in order to reduce signal transmission delays caused by the finer interconnections, it is proposed to adopt an interconnection structure including a low-permittivity layer (“low-K layer”) as the interlevel dielectric film, together with the formation of the embedded interconnection structure.
Conventionally, two methods are proposed and implemented for using the low-K layer as the interlevel dielectric film and forming the embedded interconnection structure based on the dual damascene technique.
First Conventional Method
Referring to
FIGS. 1A
to
1
H, a conventional method (hereinafter referred to as “the first conventional method”) for the formation of the low-K layer as the interlevel dielectric film and the embedded interconnection structure based on the dual damascene technique will be described. These figures are sectional views consecutively illustrating the respective steps of the process for formation of the embedded interconnection structure by using the first conventional method.
In the first conventional method, through-holes are first formed, and then an interconnection trench structure for receiving therein upper-level interconnections is formed, as will be described hereinafter.
First, as shown in
FIG. 1A
, a P-type SiN film (referred to as P-SiN film hereinafter)
14
having a film thickness of 50 nm is formed by a plasma CVD method as an anti-diffusion layer for suppressing diffusion of Cu atoms in a Cu layer
12
formed as lower-level interconnections. A low-K layer
16
having a film thickness of 700 nm is then formed as an interlevel dielectric film. A P-SiO
2
film
18
having a film thickness of 100 nm is further formed thereon by a plasma CVD method.
Thereafter, as shown in
FIG. 1B
, a first anti-reflection coat (first ARC film)
20
having a film thickness of 100 nm is formed on the P-SiO
2
film
18
. A photoresist film having a film thickness of 600 nm is formed on the first ARC film
20
by coating, followed by selectively etching thereof to form an etching mask
22
having a through-hole pattern.
Then, the first ARC film
20
and the P-SiO
2
film
18
are selectively etched by a dry-etching technique using the etching mask
22
and a fluorocarbon gas. Next, a mixture of nitrogen and hydrogen gases is used to remove the etching mask
22
of the photoresist, the first ARC film
20
below the etching mask
22
, and part of the low-K film
16
where the P-SiO
2
film
18
is etched. By this etching, the etching mask
22
of the photoresist film and the first ARC film
20
are completely removed to form through-holes
24
exposing P-SiN film
14
therethrough.
Thereafter, as shown in
FIG. 1D
, a second ARC film
26
is formed on the entire surface of the P-SiO
2
film
18
while simultaneously filling the through-holes
24
. Then, a photoresist film
28
is formed on the second ARC film
26
by coating.
As shown in
FIG. 1E
, the photoresist film
28
is then patterned, whereby an etching mask
30
having an interconnection pattern of the upper-level interconnections is formed.
Then, the second ARC film
26
and the P-SiO
2
film
18
are subjected to selective etching using the etching mask
30
and a fluorocarbon gas as the etching gas, followed by selective etching of the low-K film
16
. This etching allows the photoresist mask
30
and the first ARC film
20
underlying the same to be completely removed, as shown in
FIGS. 1F and 1G
.
Thereafter, the P-SiN layer
14
on the Cu layer
12
is etched, thereby forming through-holes
32
for exposing therethrough the Cu layer
12
, as shown in FIG.
1
H.
Then, a barrier metal layer not shown is formed on the inner wall of the through-holes
32
and the interconnection trenches
34
as well as on top of the P-SiO
2
film
18
, and further a Cu layer is deposited thereon, thereby completely filling the through-holes
32
and the interconnection trenches
34
with the Cu layer.
After removing the Cu layer and the barrier metal layer on top of the P-SiO
2
film
18
by a CMP method, embedded upper-level interconnections connected to the lower-level Cu layer
12
via the through-holes
32
can be formed.
Second Conventional Method
Referring to
FIGS. 2A
to
2
I, another conventional method (hereinafter referred to as “second conventional method”) for formation of the embedded interconnection structure based on the dual damascene method, which uses the low-K layer as the interlevel dielectric film, will be described. These figures are sectional views of the respective steps of the process for forming the interconnections by using the second conventional method.
In the second conventional method, the interconnection trenches are first formed and then the through-holes are formed, as will be described hereinafter.
As shown in
FIG. 2A
, there are consecutively formed, on a Cu layer
36
formed as the lower-level interconnections, a P-SiN film
38
having a film thickness of 50 nm as the anti-diffusion film for the Cu atoms, a low-K layer
40
having a film thickness of 700 nm as an interlevel dielectric film and a P-SiO
2
film
42
and P-SiN film
44
, each having a film thickness of 50 nm, as a hard mask film.
Then, as shown in
FIG. 2B
, a 400-nm-thick photoresist film is formed on the P-SiN film
44
by coating, followed by selective etching thereof to form an etching mask
46
having an interconnection pattern of the upper-level interconnections. Prior to the formation of the photoresist film, an ARC film may be formed.
The etching mask
46
is used to etch the P-SiN film
44
as shown in
FIG. 2C
, thereby exposing part of the P-SiO
2
film
42
. Trenches
47
are then formed which have the same width as the interconnections of the upper-level interconnection structure.
Then, as shown in
FIG. 2D
, the P-SiN film
44
is exposed by removing the etching mask
46
by an O
2
plasma ashing method.
As shown in
2
E, a photoresist film is then formed by coating and patterned by etching, thereby forming an etching mask
48
having a through-hole pattern.
Referring to
FIGS. 2F
, the P-SiO
2
film
42
is then etched to form through-holes
50
which expose part of the low-K layer
40
.
Next, the etching mask
48
is used to etch the low-K layer
40
, thereby forming through-holes
52
A for exposing the P-SiN film
38
. Subsequently, the etching mask of the photoresist film is removed at the same time with the low-K film, as shown in FIG.
2
G.
The P-SiN film
44
is then used as the etching mask to etch the P-SiO
2
film
42
and the low-K layer
40
, whereby interconnection trenches
54
for the upper-level interconnections are formed, as shown in FIG.
2
H.
Further, the low-K layer
40
is used as the etching mask to etch the P-SiN film
38
, whereby through-holes
52
are formed which communicate to the interconnection trenches
54
and exposing part of the Cu layer
36
, as shown in FIG.
21
.
Then, a barrier metal layer not shown is formed on the inner walls of the through-holes
52
and the interconnection trenches
54
as well as on top of the P-SiO
2
film
44
. A further Cu layer is deposited, thereby forming a Cu layer having a sufficient thickness for filling the through-holes
52
and the interconnection trenches
54
.
After the Cu layer and the barrier metal layer on top of the P-SiO
2
film
44
are removed by a CMP method, embedded interconnections connected to lower-level Cu layer
36
through via plugs can be formed.
The first and second conventional methods as described above have the following problems, however.
In the case of the first conventional
Hayes & Soloway PC
Lee Hsien-Ming
NEC Corporation
Pham Long
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