Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame
Reexamination Certificate
2000-04-18
2002-10-29
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With structure for mounting semiconductor chip to lead frame
C257S254000, C257S255000, C257S415000, C257S417000, C257S418000
Reexamination Certificate
active
06472730
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device capable of protecting a semiconductor element from circuit analysis, by the use of electrical properties of transistors which change as a result of warping or otherwise distorting the semiconductor element, and also to a method of manufacturing such a semiconductor device.
BACKGROUND OF THE INVENTION
Conventionally, a semiconductor element chip (hereinafter, will be simply referred to as “a chip”) containing transistors, as well as circuitry including an IC (Integrated Circuit) or an LSI (Large Scale Integration) circuit, is sealed in, for example, a plastic package before actual used as a semiconductor device. The sealing is provided in view of protection from environment and so as to enable easy handling of the semiconductor element chip.
FIG. 16
shows such an example of a package-type semiconductor device
101
in which a chip
102
containing an LSI circuit as part of its circuitry is sealed in an epoxy resin package
108
. The chip
102
is secured firmly on a die-pad
103
by silver paste
104
, and provided with pads
105
where the chip
102
is connected via gold wire bonds
106
to lead wires
107
which are in turn connected to components external to the package
108
.
A typical package-type semiconductor device is manufactured in the following manner. First, the securing surface of the die-pad
103
is coated with the silver paste
104
on which the chip
102
is placed, and the whole piece is pressed while being heated at 160° C. to 170° C., so that the silver paste
104
solidifies with heat, thereby securing the chip
102
onto the die-pad
103
. Thereafter, the pads
105
of the chip
102
are coupled to the lead wires
107
by the gold wire bonds
106
. The manufacturing process completes as a package
108
is formed by sealing the chip
102
in epoxy resin.
Currently, in most cases, the chip
102
is at least 200 &mgr;m thick, and is normally secured on the die-pad
103
in a flat state so as to prevent deterioration of its properties.
Japanese Laid-Open Patent Application No. 5-211262/1993 (Tokukaihei 5-211262; published on Aug. 20, 1993) discloses a technology (will be referred to as technology 1) used for a resin seal-type semiconductor device, which is a package-type semiconductor device of the foregoing kind. According to the technology, a heat spreader is provided under a pellet support (corresponds to the die-pad
103
) on which a semiconductor pellet (corresponds to the chip
102
) is mounted, thereby reducing thermal resistance and allowing high power-consuming products to be offered in plastic packages. Further, the technology enables the resin to have a uniform thickness, thereby reducing the likelihood of cracks and warps developing in the package. The technology successfully gives products improved reliability.
Further referring to a package-type semiconductor device of the foregoing kind, Japanese Laid-Open Patent Application No. 64-15957/1989 (Tokukaisho 64-15957; published on Jan. 19, 1989) discloses a technology (will be referred to as technology 2) used for a package in which pressure is exerted to the chip
102
. According to the technology, gas or liquid is sealed in a semiconductor package together with an NMOS semiconductor element chip (corresponds to the chip
102
), so as to exert mechanical pressure (stress) to the chip, thereby increasing current and improving the performance of the semiconductor element.
In reference to technology 2 above, although not related to semiconductor elements, Japanese Laid-Open Patent Application No. 5-93659/1993 (Tokukaihei 5-93659; published on Apr. 16, 1993) and other documents disclose a sensor that works based on the stress exerted to various kinds of resistor elements. The sensor works based on the electric resistance of a glass layer which changes with distortion.
Incidentally, the package-type semiconductor device
101
leaves the integrated circuit contained in the chip
102
sealed in the semiconductor device
101
relatively susceptible to analysis. To perform analysis on the chip
102
, the package
108
is first unsealed to allow observation of the chip
102
. Normally, the chip
102
is coated with a polyimide film (not shown) having a thickness of 50 &mgr;m to 100 &mgr;m to prevent malfunction caused by &agr; rays. Further, when the chip
102
is sealed, the package
108
is formed by covering the chip
102
with epoxy resin or other materials as mentioned in the foregoing. Therefore, simply unsealing the package
108
is not enough to observe the chip
102
through microscope, let alone to analyse the integrated circuit.
However, the polyimide film and epoxy resin can be removed using an etchant containing oleum and sulfuric acid as its components. Once the resin and other coverings are removed using etchant, the chip
102
itself is susceptible to any kind of analysis from external observation to circuit analysis whereby properties can be measured through a probe directly in contact with the chip
102
.
Further, the packaged chip
102
is 200 &mgr;m thick or thicker; therefore, the packaged chip
102
is sealed in a flat state in the package
108
, and even after the coverings are removed for analysis, the chip
102
still retains the flat state, allowing the integrated circuit contained in the chip
102
to operate normally with the same properties as when it is packaged.
In short, the structure and packaging method of the conventional semiconductor device
101
do not go far enough to prevent performing analysis on the integrated circuit contained in the chip
102
from which the resin is removed and is laid alone, failing to offer protection to secret information.
Technology 1, although having successfully improved the reliability and performance of semiconductor devices, does not pay attention at all to the prevention of analysis of the chip
102
. Similarly, technology 2, although pressure is applied to the chip
102
in the package, does not pay attention at all to the prevention of analysis of the chip
102
, rendering the chip
102
readily available for analysis once the chip
102
is separated from all the other components and laid alone. Further, the documents related to distortion sensors deal with a different technical field, and do not disclose nor suggest the prevention of analysis.
SUMMARY OF THE INVENTION
In view of the foregoing problem, the present invention has an object to offer a package-type semiconductor device capable of providing a high level of protection from circuit analysis to an integrated circuit contained in a semiconductor element chip sealed in a package, and also a method of manufacturing such a semiconductor device.
In order to solve the foregoing problems, the semiconductor device in accordance with the present invention includes: a semiconductor element with an integrated circuit; and a package for sealing the semiconductor element therein, so as to be connected to an external circuit for use, wherein
the semiconductor element is secured in the package in a predetermined distorted state, and
the semiconductor element operates normally only in the distorted state.
With the arrangement, the semiconductor element operates normally only in the predetermined distorted state; therefore, once the semiconductor element is separated from the semiconductor device and thereby released from the distorted state, the semiconductor element dose not operate normally. This ensures that the semiconductor element is protected from circuit analysis, and thereby ensures that the secret information of the semiconductor element is protected.
The method of manufacturing a semiconductor device in accordance with the preset invention, in order to solve the foregoing problems, is such that
in the step of sealing a semiconductor element with an integrated circuit in a package, a semiconductor element that operates normally only in a predetermined distorted state is secured and thereafter sealed in the package in the distorted state.
According to the method, a semiconductor element that operates no
Ban Hiroshi
Nakano Akihiko
Ohmi Toshinori
Takeda Tadao
Unno Hideyuki
Chu Chris C
Lee Eddie
Sharp Kabushiki Kaisha
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