Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-04-07
2001-06-26
Lebentritt, Michael (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S241000, C438S253000, C438S396000, C438S618000
Reexamination Certificate
active
06251721
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device suitable for high integration and a method of manufacturing the same, particularly to a semiconductor device suitably applicable to a semiconductor memory, such as a DRAM or a flash memory, having an element region and a peripheral circuit region.
2. Description of the Related Art
In recent years, there is a strong tendency to demand not only high integration but also a higher added value of a semiconductor device. For example, for a DRAM hybrid chip having a memory cell and a logic circuit (a peripheral circuit of the memory cell), which has received a great deal of attention as a semiconductor memory in a new field, a technique of forming a metal silicide that reduces the resistance value in the source and the drain of a transistor constructing the logic circuit is indispensable. In application of this technique, however, a fundamental problem is posed in which no metal silicide can be used for the source and the drain of the transistor constructing the memory cell of a DRAM from the viewpoint of refresh characteristics. Hence, for the source and the drain of the transistor, the memory cell side and the logic circuit side must be independently formed.
However, the above-described technique has an aspect inconsistent with the requirement of a highly integrated memory cell. More specifically, as the degree of integration rises, the alignment margin of contact holes becomes strict. To relax it, a nitride film with an etching rate lower than that of an oxide film is formed as a passivation film covering the transistor, and a borderless contact technique (BLC) or a self-alignment contact technique (SAC) of forming a contact hole in self-alignment is used. In this example, use of the self-aligning technique described above poses a problem to be described below in detail.
When the memory cell size is reduced by high integration, the distance between adjacent gate electrodes of the memory cell also shortens. In this case, as shown in
FIG. 31A
, when the distance between gate electrodes
301
shortens, an element interval
302
between the gate electrodes
301
becomes zero due to a BLC or SAC nitride film
306
. This disables BLC or SAC as a preprocess for formation of a metal silicide, nothing to say of metal silicide formation.
As a countermeasure against this problem, a technique has been proposed in which after formation of the gate electrodes
301
, a thin nitride film
303
for SAC, which has a thickness of about 30 nm, and an oxide film having a predetermined thickness are sequentially formed, and then a side wall
304
is formed on the entire surface of the structure by anisotropic etching, as shown in FIG.
31
B. In this case, however, since a metal silicide need be formed on only the transistor on the logic circuit side, the source/drain surface of the transistor on the logic circuit side must be exposed by etching while masking the structure on the memory cell side. After formation of a metal silicide, a BLC nitride film
305
is formed. At this time, since the interval between the gate electrodes
301
is small, the gap between the side walls
304
is filled with the nitride film
305
, as shown in
FIG. 31B
, so the nitride film
305
is substantially very thick when viewed from the upper side in forming a contact hole. This disables SAC on the memory cell side.
As described above, the requirement for reduction of resistance in the transistor of the logic circuit and that for an increase in the degree of integration of the entire memory cell portion and the logic circuit portion have tradeoff relationships. It is very difficult to meet these requirements simultaneously.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device in which, when the first region is a memory cell region, and the second region is a peripheral circuit region, silicidation of the source and the drain of a transistor in the peripheral circuit region and the self-alignment technique such as BLC or SAC are simultaneously used to enable an increase in the degree of integration and improvement of performance (improvement of operation speed) of a semiconductor memory having a metal silicide on the transistor of the logic circuit, and a method of manufacturing the semiconductor device.
In order to achieve the above object, the present invention has the following aspects.
According to the first aspect, a method of manufacturing a semiconductor device, comprises the steps of forming gate electrodes in a first region over a semiconductor substrate and one gate electrode in a second region over said semiconductor substrate, and then forming first impurity diffusion layers on both sides of said gate electrodes in said first and second regions; forming a first passivation film in said first and second regions; forming an insulating film in said first and second regions, processing said insulating film in said second region to form a side wall on both sides of the gate electrode in said second region to expose a surface of said semiconductor substrate on both sides of said side wall; forming, in said semiconductor substrate exposed on both sides of said side wall, a second impurity diffusion layer partially to overlap said first impurity diffusion layer; forming a second passivation film in said first and second regions; and forming a first connection hole for exposing said first impurity diffusion layer in said first region, and a second connection hole for exposing said second impurity diffusion layer in said second region, by using said first and second passivation films.
According to the second aspect, a method of manufacturing a semiconductor device, comprises the steps of forming gate electrodes in a first region over a semiconductor substrate and one gate electrode in a second region over said semiconductor substrate, and then forming first impurity diffusion layers on both sides of said gate electrodes in said first and second regions; forming a first passivation film in said first and second regions; forming an insulating film in said first and second regions, processing said insulating film in said second region to form a side wall on both sides of the gate electrode in said second region to expose a surface of said semiconductor substrate on both sides of said side wall; forming, in said semiconductor substrate exposed on both sides of said side wall, a second impurity diffusion layer partially to overlap said first impurity diffusion layer, and then removing said insulating film in said first region and said side wall in said second region; forming a second passivation film in said first and second regions; and forming a first connection hole for exposing said first impurity diffusion layer in said first region, and a second connection hole for exposing said second impurity diffusion layer in said second region, by using said first and second passivation films.
According to the third aspect, in a semiconductor device having first and second regions in which elements having gate electrodes with sources/drains are formed, a first passivation film is formed to a thickness not to fill spaces between said gate electrodes in said first region, and an insulating film is formed on said first passivation film to fill said spaces between said gate electrodes in said first region, a side wall is formed on only the gate electrode in said second region, a metal silicide film is formed on the source/drain in said second region, and a second passivation film is formed to cover said gate electrode in said second region including said side wall, and first and second connection holes are formed to expose parts of said first and second passivation films from side surfaces, and an interconnection is formed to connect electrically the source/drain in said first region and said metal silicide film through said first and second connection holes.
According to the fourth aspect, in a semiconductor device having first and second regions in which elements having gate elec
Hashimoto Koichi
Kanazawa Kenichi
Katsube Masaki
Takao Yoshihiro
Armstrong Westerman Hattori McLeland & Naughton LLP
Fujitsu Limited
Lebentritt Michael
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