Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-07-24
2004-01-20
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S261000, C438S238000
Reexamination Certificate
active
06680230
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based on and claims the benefit of priority from prior Japanese Patent Applications No. 2001-225027, filed on Jul. 25, 2001 and No. 2001-229409, filed Jul. 30, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor devices with a plurality of types of transistors integrated together and, more particularly, to methodology of fabricating a semiconductor device including an array of non-volatile memory cells formed of transistors, also known as “memory transistors.”
2. Description of the Related Art
Nonvolatile semiconductor memory devices including but not limited to “flash” electrically erasable programmable read only memory (EEPROM) chips of the NAND cell type are typically designed to employ memory transistors with metal insulator semiconductor field effect transistor (MISFET) structures. These memory transistors each have a lamination or multilayer structure of an electrically isolated gate, typically termed “floating” gate, for use as a charge storage layer and a control gate over a semiconductive chip substrate. A dielectric insulating film for use as a gate insulator (gate insulator film) is interposed between the floating gate and the substrate. This gate insulator film is formed of a tunnel dielectric film with a thickness of approximately 8 nanometers (nm) in light of carrier injection and release (charge and discharge) between the substrate and the floating gate and also the data retaining characteristics required.
On the other hand, peripheral circuitry for performing data write/erase/read control of a cell array includes high voltage-driven transistors to which a potentially increased or “raised” voltage directly relating to write and erase operations is given and low voltage-driven transistors operable with a power supply voltage. The high voltage transistors make use of a gate insulator film as thin as about 35 nm to provide enhanced durability against high voltages applied thereto. The low voltage transistors use a thinner gate insulator film.
These three kinds of gate insulator films—that is, the tunnel dielectric, high voltage transistor gate insulator, and low voltage transistor gate insulator films—are obtainable for example by a process which follows. Firstly, form by thermal oxidation a gate oxide film with a thickness of 3 nm in a cell array region of a silicon substrate. Then, let the substrate surface be exposed at its selected portion in a high voltage transistor region. Next, perform thermal oxidation again to thereby form a gate oxide film which is about 30 nm thick. Subsequently, expose a surface portion of the substrate in a low voltage transistor region and then perform thermal oxidation, thereby forming a gate oxide film of about 5 nm thickness. Through repeated effectuation of thermal oxidation processes, a gate oxide film of about 8 nm thick is finally obtained in the cell array region, with a gate oxide film of about 35 nm thick being formed in the high voltage transistor region.
However, such method for sequentially forming the gate oxide films in the respective circuit regions is under strict and severe requirements for film thickness controllability. In particular, the tunnel dielectric film for use in memory transistors is sensitive to even a small mount of slight film thickness variation in view of the fact that this film directly affects the data write/erase/retain characteristics. This makes it difficult to obtain higher production yields and increased reliability.
Additionally, it is also important for the memory transistor tunnel dielectric film to offer superior film quality other than the accurate thickness controllability. It has been traditionally known among those skilled in the semiconductor device art that film quality degradation occurs due to some causes, one of which is contamination from resist masks. With the method having the steps of forming an oxide film for later use as the tunnel dielectric film of the cell array region, directly forming on its surface a resist mask, and then etching a portion of the tunnel dielectric film of peripheral circuitry to thereby expose its corresponding substrate surface, it is impossible to obtain any intended tunnel dielectric film of high quality.
Methods for precluding resist contamination of the tunnel dielectric film of the cell array have been proposed until today, one of which is disclosed, for example, in Japanese Patent Publication (Kokoku) No. 8-21636. With this method as taught thereby, immediately after having formed a desired tunnel dielectric film in the cell array region, deposit thereon a polycrystalline silicon or “poly-silicon” film for later use as portions of gate electrodes. Then, form a resist mask pattern having an opening in a peripheral circuit region. Next, remove by etching the polysilicon film and its underlying gate insulator film, thus forming a gate insulator film of the peripheral circuitry.
If the gate insulator films for use in high-voltage and low-voltage transistors of the peripheral circuitry are formed sequentially while letting the cell array region's tunnel dielectric film be covered with the polysilicon film in this way, then the tunnel dielectric is no longer contaminated while guaranteeing that no appreciable film thickness changes take place even during thermal oxidation processes to be later performed. This enables achievement of good thickness controllability and improved film quality.
Unfortunately, even the method of making the gate insulator film of peripheral circuitry while letting the tunnel dielectric film be covered or coated with the polysilicon film is encountered with problems that follow. A first problem is that even in the state that a polysilicon film is formed for use as part of floating gates, memory transistors can decrease in reliability if its following thermal processing is done at high temperatures for an increased length of time period.
FIG. 20
shows a typical pattern of threshold voltage variation or change as measured when a memory transistor is repeatedly subject to write and erase cycles.
As shown in
FIG. 20
, in regard to both the write state (i.e. electron is injected to a floating gate resulting in a threshold voltage being made higher) and the erase state (the stored electron is released out of the floating gate resulting in the threshold voltage being lowered), the threshold voltage tends to potentially rise up with an increase in write/erase cycle number. When compared to the case (indicated by solid lines in
FIG. 20
) where thermal processing after floating gate formation is carried out at relatively low temperatures for a shortened time period, the tendency becomes more significant when the thermal process is done at higher temperature for a longer time period (indicated by dotted lines). As a example, successful fabrication of a 30-nm thick gate insulator film for use in high voltage transistors requires thermal oxidation at 1150° C. for 200 seconds, or more or less. This would result in a decrease in reliability of the memory transistors which are covered by the polysilicon film.
A second problem faced with the above-noted prior known method lies in occurrence of re-diffusion of doped impurity due to thermal processing. More specifically, when doping impurity ions into the cell array region for transistor threshold voltage adjustment purposes prior to formation of the gate insulator film of the peripheral circuitry, in particular, during the high-temperature/long-time thermal oxidation process for forming the gate oxide film of high voltage transistors, rediffusion of doped impurity can take place. This disables achievement of any desired impurity concentration profile in the cell array region. Especially in the cell array with a layout of micropatterned ultra-fine memory transistors, it is desired to accurately control the carrier concentration profile of an impurity doped in transistor channel in order to reduce the so
Arai Fumitaka
Arai Norihisa
Aritome Seiichi
Shimizu Akira
Shirota Riichiro
Lindsay, Jr. Walker L.
Niebling John F.
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