Semiconductor device and method of fabricating the same

Details Semiconductor device and method of fabricating the same Semiconductor device and method of fabricating the same

2002-05-09

2003-10-28

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S202000

Reexamination Certificate

active

06638806

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method of fabricating a semiconductor device, and more specifically, it relates to a method of fabricating a BiCMOS (Bipolar-Complementary Metal Oxide Semiconductor) device having a bipolar transistor and a CMOS (Complementary Metal Oxide Semiconductor) transistor. The present invention also relates to a semiconductor device obtained by this method.
2. Description of the Prior Art
A BiCMOS device provided with both of a bipolar transistor having high-speed performance and excellent drivability and CMOS transistors allowing high integration and having low power consumption is generally employed as a semiconductor device.
FIG. 82
is a sectional view of a conventional BiCMOS device.
First, a bipolar transistor part is described.
An N
+
-type embedded layer
3
is formed on a P-type silicon substrate
1
, and an N-type epitaxial layer
4
is further formed on the upper surface thereof. A field oxide film
7
, a P-type well region
12
and a P-type isolation region
5
are formed for element isolation. A base region, consisting of a P-type intrinsic base region
16
and a P
+
-type external base region
18
, and an N
+
-type emitter region
19
are formed on a surface part of the N-type epitaxial layer
4
. The field oxide film
7
is held between an N
+
-type collector region
2
and the epitaxial layer
4
. The N
+
-type collector region
2
reaches the N
+
-type embedded layer
3
.
A P
+
-type external base draw-out electrode
13
is provided on the external base region
18
. The external base draw-out electrode
13
extends onto the field oxide film
7
. An N
+
-type emitter electrode
20
is formed in an emitter opening of the external base draw-out electrode
13
. The emitter electrode
20
and the external base draw-out electrode
13
are electrically isolated from each other by side wall oxide films
17
and an oxide film
14
. An interlayer isolation film
32
covers the external base draw-out electrode An interlayer isolation film
32
covers the external base draw-out electrode
13
, the emitter electrode
20
and the N
+
-type collector region
2
. Contact holes
6
are formed in the interlayer isolation film
32
. Metal wires
33
(aluminum wires, for example) are formed in the contact holes
6
.
CMOS transistor parts are now described.
First, a PMOS (P channel Metal Oxide Semiconductor) part is described. An N
+
-type embedded layer
3
is formed on the P-type silicon substrate
1
. An N-type well region
10
is formed on the upper surface of the N
+
-type embedded layer
3
. A field oxide film
7
is formed for element isolation. A gate electrode
22
(N
+
-type polysilicon film, for example) is formed on the surface of the N-type well region
10
. P
+
-type source/drain regions
31
are formed on the surface of the N-type well region
10
on both sides of the gate electrode
22
. The interlayer isolation film
32
covers the P
+
-type source/drain regions
31
and the gate electrode
22
. Contact holes
6
are formed in the interlayer isolation film
32
. Metal wires
33
(aluminum wires, for example) are formed in the contact holes
6
.
An NMOS (N channel Metal Oxide Semiconductor) part is now described. A P-type isolation region
5
is formed on the P-type silicon substrate
1
. A P-type well region
12
is formed on the upper surface of the P-type isolation region
5
. A field oxide film
7
is formed for element isolation. A gate electrode
22
(N
+
-type polysilicon film) is formed on the surface of the P-type well region
12
. N
+
-type source/drain regions
30
are formed on the surface of the P-type well region
12
on both sides of the gate electrode
22
. The interlayer isolation film
32
covers the N
+
-type source/drain regions
30
and the gate electrode
22
. Contact holes
6
are formed in the interlayer isolation film
32
. Metal wires
33
(aluminum wires, for example) are formed in the contact holes
6
.
A method of fabricating the BiCMOS device shown in
FIG. 82
is now described.
Referring to
FIG. 70
, the N
+
-type embedded layers
3
, the P-type isolation regions
5
, the N-type epitaxial layer
4
, the field oxide films
7
and the N
+
-type collector region
2
are formed on the P-type silicon substrate
1
. Then, an underlayer oxide film
8
is formed on the surface of the silicon substrate
1
. The thickness of the underlayer oxide film
8
is 30 nm, for example. A resist mask
9
is formed on the silicon substrate
1
by patterning. N-type impurities
111
are implanted into a region for forming a PMOS transistor through the resist mask
9
. The impurities are implanted in a divided manner (phosphorus is implanted at 400 KeV by 2×10
12
cm
−2
and at 180 KeV by 4×10
12
cm
−2
and boron is implanted at 20 KeV by 3×10
12
cm
−2
, for example) for forming the N-type well region
10
(see FIG.
71
). Thereafter the resist mask
9
is removed.
Referring to
FIG. 71
, a resist mask
11
is formed on the silicon substrate
1
by patterning. A P-type impurity
222
is implanted into a region for forming an NMOS transistor through the resist mask
11
, thereby forming the P-type well region
12
(see FIG.
72
). Also in this case, the impurity is implanted in a divided manner (boron is implanted at 300 KeV by 1×10
12
cm
−2
, at 160 KeV by 3×10
12
cm
−2
and at 50 KeV by 6×10
12
cm
−2
, for example). Thereafter the resist mask
11
is removed.
Referring to
FIGS. 71 and 72
, the underlayer oxide film
8
is removed and a polysilicon film
13
is deposited on the overall surface by 150 nm, for example, and a P-type impurity is implanted into the polysilicon film
13
(BF
2
is implanted at 40 KeV by 4×10
15
cm
−2
, for example). Then, a CVD (Chemical Vapor Deposition) oxide film
14
is deposited on the overall surface by 300 nm, for example.
Referring to
FIGS. 72 and 73
, the CVD oxide film
14
and the polysilicon film
13
are patterned by etching, for forming the external base electrode
13
. At this time, the surfaces of the collector region
2
, the emitter opening, the N-type well region
10
and the P-type well region
12
are etched. Referring to
FIG. 73
, symbols A-
1
, B-
1
, C-
1
and D-
1
denote the collector region
2
, the emitter opening, the N-type well region
10
and the P-type well region
12
respectively.
Referring to
FIG. 74
, a resist mask
15
is formed on the silicon substrate
1
by patterning. A P-type impurity
333
is implanted into the emitter opening (BF
2
is implanted at 25 KeV by 8×10
13
cm
−2
, for example) through the resist mask
15
, for forming the intrinsic base region
16
(see FIG.
75
).
Referring to
FIG. 75
, a CVD oxide film (not shown) is formed on the overall upper surface of the silicon substrate
1
and dry-etched, for forming the side wall oxide films
17
in the emitter opening.
Referring to
FIG. 76
, a polysilicon film for defining the emitter electrode
20
is deposited on the overall surface by 150 nm, for example, and an N-type impurity is implanted into this polysilicon film (arsenic is implanted at 50 KeV by 1×10
16
cm
−2
, for example). After this impurity implantation, annealing is performed for diffusing arsenic into the intrinsic base region
16
from the polysilicon film, thereby forming the emitter region
19
. At this time, boron diffuses from the external base electrode
13
, for forming the external base region
18
.
While diffusion of boron takes place also in heat treatment preceding this annealing step, such diffusion is not illustrated. Then, the polysilicon film is etched for forming the emitter electrode
20
. At this time, the surfaces of the collector region
2
, the N-type well region
10
and the P-type well region
12
are etched. Referring to
FIG. 76
, symbols A-
2
, C-
2
and D-
2
denote the collector region
2
, the N-type well region
10
and the P-type w

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