Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-10-04
2002-01-01
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S592000
Reexamination Certificate
active
06335250
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a MOS transistor and, more particularly to a semiconductor device used for MOS transistors incorporating elevated source/drain technique and a method for the manufacture of the semiconductor device.
The local interconnection layer which connects the transistors adjacent to each other in, e.g., a static random access memory (SRAM) has so far been formed as follows:
First, a plurality of transistors are formed. Specifically, as shown in
FIG. 7
, an element isolation region
72
is formed in a surface region of a silicon substrate
71
to define a plurality of element formation regions
72
in the silicon substrate
71
. Formed on each of the element regions of the silicon substrate
71
is a gate oxide film
73
, on which a gate electrode
73
is formed. On the side surfaces of the oxide film
73
and the gate electrode
73
, a gate side-wall spacer
75
is formed. After this, an impurity for forming source and drain regions is introduced into the silicon substrate
71
, and thus, a plurality of transistors are formed.
Next, a local interconnection layer is formed. Specifically, a silicon nitride film
76
is formed by deposition on the surface of the silicon substrate
71
including the gates, as shown in FIG.
8
. On the silicon nitride film
76
, a silicon oxide film
77
is formed by deposition. On the silicon oxide film
77
, a resist (not shown) is coated and then the resist film is patterned by the use of the lithography method.
Further, as shown in
FIG. 9
, using the patterned resist as a mask, only those portions of the silicon nitride film
76
and silicon oxide film
77
which lie in the local interconnection formation portion are etched to form an opening
77
a.
Next, on the silicon oxide film
77
, a metal is deposited, whereby the opening
77
a
is filled up with the metal. Thereafter, the metal lying on the silicon oxide film
77
is removed by the use of the CMP (Chemical Mechanical Polishing) method, thus forming a local interconnection layer
78
in the opening
77
a.
A local interconnection manufacturing method as mentioned above comprises a very complicated manufacturing step, that is, the step of depositing insulating materials on the silicon substrate
71
and then forming the opening
77
a
in the thus deposited insulation material.
Further, when the metal is removed by the use of CMP, the silicon oxide film
77
is polished, and thus, there is the possibility that even the transistors may be removed. Due to this, in the formation of the local interconnection layer
78
, the silicon oxide film
77
must be formed thick. As a result, the aspect ratio of the opening
77
a
is increased, which leads to the problem that, in proportion to the thus increased thickness of the insulation film, the formation of the opening becomes more difficult.
Further, when the silicon nitride film
76
and the silicon oxide film
77
are etched to form the opening
77
a,
even the element isolation region
72
is etched in some cases. As a result, the surface of the element isolation region
72
is positioned below the bottom surfaces of the source and drain regions in the silicon substrate
71
in some cases. No current flows between the p-type region and the n-type region when a reverse bias is applied across the regions, however, in case the surface of the element isolation region
72
is lowered below the bottom surfaces of the source and drain regions, then leakage current flows into the silicon substrate
71
, thus causing the problem of lowering the functions of the elements.
As described above, the conventional technique has the disadvantage that the local interconnection forming step is complicated, and the formation of the opening is difficult.
BRIEF SUMMARY OF THE INVENTION
The present invention has been made in order to achieve a solution to the above-mentioned disadvantage, and it is an object of the invention to provide a semiconductor device and a method for the formation thereof in which the step of forming the local interconnection layer is easy to execute.
According to a first aspect of the present invention, there is provided a semiconductor device comprising a gate electrode of a transistor formed on a surface of a semiconductor substrate; a source/drain region of the transistor, the source/drain region being at a side of the gate electrode of the transistor, a portion of the source/drain region being positioned higher than the surface of the semiconductor substrate; and an interconnection layer comprised of a silicide layer which is formed on an insulation film formed in the surface region of the semiconductor substrate, the interconnection layer connecting the source/drain region of the transistor to another active region and being formed at the same time as a silicide layer on the portion of the source/drain region of the transistor.
In the semiconductor device according to the first aspect of the present invention, the insulation film may comprise an element separation film formed in the surface region of the semiconductor substrate. The element separation film may comprise a shallow trench isolation film.
In the semiconductor device according to the first aspect of the present invention, the transistor may be of type of elevated source and drain.
In the semiconductor device according to the first aspect of the present invention, the silicide layer of the interconnection layer may be a silicide layer of a refractory metal. The silicide layer of the refractory metal may include a silicide layer of titanium (Ti), a silicide layer of cobalt (Co), a silicide layer of nickel (Ni), a silicide layer of platinum (Pt), a silicide layer of tungsten (W), and a silicide layer of molybdenum (Mo).
According to a second aspect of the present invention, there is provided a semiconductor device comprising an element separation film formed in a surface region of a semiconductor substrate, defining at least two element formation regions in the surface region of the semiconductor substrate; a transistor provided in each of the element formation regions, formed on the surface of the semiconductor substrate, the transistor having a gate electrode formed on the surface region of a semiconductor substrate and a source/drain region being at a side of the gate electrode, a portion of the source/drain region being positioned higher than the surface of the semiconductor substrate; and an interconnection layer comprised of a silicide layer which is formed on the element separation film, the interconnection layer connecting the source/drain region of the transistor formed in one of the element formation regions to the source/drain region of the transistor formed in another of the element formation regions.
In the semiconductor device according to the second aspect of the present invention, the element separation film may comprise a shallow trench isolation film.
In the semiconductor device according to the second aspect of the present invention, the transistor may be of type of elevated source and drain.
In the semiconductor device according to the second aspect of the present invention, the silicide layer of the interconnection layer may be a silicide layer of a refractory metal. The silicide layer of the refractory metal may include a silicide layer of titanium (Ti), a silicide layer of cobalt (Co), a silicide layer of nickel (Ni), a silicide layer of platinum (Pt), a silicide layer of tungsten (W), and a silicide layer of molybdenum (Mo).
According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of forming a gate insulation film of a transistor on a surface region of a semiconductor substrate; forming a gate electrode on the gate insulation film; forming an insulation film covering the gate insulation film and the gate electrode; forming by deposition an amorphous semiconductor layer over the surface region of the semiconductor substrate thus formed; selectively growing the amorphous semiconductor layer to form single-crystalline sem
Kabushiki Kaisha Toshiba
Niebling John F.
Whitmore Stacy
LandOfFree
Semiconductor device and method for the manufacture thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method for the manufacture thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method for the manufacture thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2840617