Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
1999-12-28
2001-07-03
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700, C365S149000
Reexamination Certificate
active
06256237
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to an apparatus and a method for repairing a failed memory cell. More particularly, the invention relates to a semiconductor and a method for repairing a failed memory cell that directly program a fuse memory cell by a tester. Therefore, after the completion of package, the failed address can still be repair by using a high voltage circuit without being restricted by the package.
2. Description of the Related Art
For the fabrication process of a semiconductor memory device, to obtain a high yield is always important. In case that there exist significant failed memory cells in a semiconductor memory device, or even that there exists only one failed memory cell, the semiconductor memory device is undeserving as a product. While fabricating a semiconductor memory device, a device with a higher integration tends to contain more failed memory cells. Or the semiconductor memory device tends to have a higher possibility to contain failed memory cells. That is, as the integration of a semiconductor device increases, the yield is reduced.
As the technique for fabricating a semiconductor memory device becomes more and more complex, the technique for packaging is correspondingly more difficult. For example, the particles or scraps produced and remained during fabrication may inevitably cause a reduction in yield. To enhance the yield, the prior technique has developed a redundancy circuit to obtain a desired yield of semiconductor memory devices. In addition to the main memory cell array for saving binary data, a redudant memory cell array is provided to replace the failed memory cells in columns and rows of the main memory cell array. Each individual redundant memory cell is connected to individual word line and bit line. Assuming that there are thousands of failed memory cells found in the main memory cell array, these redundant memory cells can replace these failed memory cells to provide a pass or non-failure memory chip.
Using the redundant memory cells or backup memory cells to replace the failed memory cells is advantageous in enhancing the yield of memory device. However, once the amounts of the designed redundant memory cells is insufficient, that is, if the number of the failed memory cells exceeds the amount of the redundant memory cells, the device cannot be repaired to be used any more.
As mentioned above, redundant memory cells can be designed around a main memory cell array to replace the failed memory cells, so as to obtain a non-defect memory chip. The connection between the main memory cell array and the redundant memory cell is typically achieved by fuse. The fuse can be blown using a laser light beam or a current. While a failed memory cell is to be repaired, the fuse is open electrically or using laser. The fuse is remained close while no repairing work is performed.
In addition, in the circuit design of a typical semiconductor device, the fuse is used for fine tuning. Especially for a dynamic random access memory (DRAM) design, the fuse is prerequisite. The fuse is often used for redundant row and column repair and is made of polysilicon or metal. A laser is then used to program the address to be repaired.
However, during the process of repair, a laser machine is used, and the wafer is to be move for fuse location. A certain fuse is then blown to proceed the repair of the address. It is thus very time and cost consuming. In addition, after the chip is fabricated, and all the pads have been bonded to the leads of the packages, that is, after being packaged, any failed memory found afterwards can never be repaired further.
SUMMARY OF THE INVENTION
The invention provides a semiconductor memory device to repair failed memory cell via programming a fuse memory cell. The semiconductor memory cell comprises a main memory cell array, a fuse memory cell array, an address programmer, a sense amplifier, a latch and a redundant memory cell array. The main memory cell comprise multiple main memory cells, while the fuse memory cell array comprises multiple fuse memory cells. The address programmer is to receive a voltage source to program an information. A certain fuse memory cell of the fuse memory cell array corresponding to this information is programmed. The sense amplifier is coupled to the fuse memory cell array to sense and receive the repairing information of the fuse memory cell array. The latch is coupled to the sense amplifier to receive and latch up the repairing information from the sense amplifier. The redundant memory cell array comprises multiple redundant memory cells and is coupled to the latch. According to the repairing information of the latch, the redundant memory cell array is to repair the failed memory cells in the main memory cell array.
The invention also provides another semiconductor memory device to repair failed memory cells by programming a fuse memory cell. The semiconductor memory device comprises an address buffer, a main memory cell array, a built-in self testing unit, data comparator, a fuse memory cell array, an address programmer and a latch. The address buffer is used to receive an address information. The main memory cell array and the fuse memory cell array comprise multiple main memory cells and multiple fuse memory cells, respectively. The main memory cell array is coupled to the address buffer to output the main memory cell address information corresponding to the address information from the address buffer. The built-in self testing unit stores the original address information for all the main memory cells in the main memory cell array. The built-in self testing unit outputs an original address information of the main memory cells corresponding to the address information. The data comparator is coupled to both the main memory cell array and the built-in self testing unit to receive and compare the address information and the original address information of the main memory cells. When the address information is different from the original address information, an error address information is output. The address programmer is coupled to the voltage source, the address buffer and the data comparator. According to the address information and the error address information, a repair address information is output to the fuse memory cell array to program the fuse memory cell corresponding to the repair address information. The latch is coupled to the fuse memory cell array to latch up the repair address information from the fuse memory cell array, and to deliver the repair address information to the main memory cell array. Thus, the failed memory cell in the main memory cell array corresponding to the repair address information is repaired.
The invention thus further provides a method for repairing a failed memory cell using programming a fuse memory cell. A first fuse memory cell and a second memory cell of a word line in the fuse memory array are turned on. A high voltage is applied to breakdown the ONO of the first fuse memory cell. The first fuse memory cell and the second fuse memory cells are then precharged to a logic state. Each time when the voltage source is raised, the first fuse memory cell and the second fuse memory cell are turned on repeatedly and the step of breaking down of the ONO of the first fuse memory cell is repeated. Meanwhile, the output address information of the first and the second fuse memory cells are latched. When the address information of the main memory cell array matches the output address information, the redundant memory cell of the redundant memory cell array corresponding to the output address information is turned on. The failed memory cell of the main memory cell array is thus repaired via the redundant memory cell of the redundant memory array.
Another method to repair a failed memory cell by programming a fuse memory cell is also provided in this invention. According to an address information, the main memory cell array generates a corresponding main memory cell address information. This main memory cell address in
Ho Ming-Jing
Jung Le-Tien
Charles C. H. Wu & Associates
Ho Hoai V.
Nelms David
United Microelectronics Corp.
Wu Charles C. H.
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