Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-06-17
2004-01-27
Smith, Matthew (Department: 2826)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000, C438S299000, C438S301000, C257S069000, C257S199000, C257S204000, C257S288000, C257S372000, C257S374000, C257S377000
Reexamination Certificate
active
06682966
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device used for a switching device, and in particular, to an MIS semiconductor device drivable at a low supply voltage and having a dynamic threshold voltage and a method for producing the same.
BACKGROUND ART
In a CMOS circuit, a power consumption is in proportion to the square of a supply voltage, and therefore reduction in the supply voltage is effective for realizing a CMOS LSI consuming less power. However, a redaction in the supply voltage reduces the driving force of transistors and thus increases a delay time period of the circuit. The problem becomes more serious as the supply voltage is reduced. Especially, it is known that the delay time period significantly increases when the supply voltage is three times the threshold voltage or less. One conceivable solution to this problem is to reduce the threshold voltage. A reduction in the threshold voltage, however, increases a leakage current when the gate is off, and therefore causes another problem that the lower limit of the threshold voltage is restricted based on the amount of tolerable leakage current when the gate is off.
In order to alleviate this problem, a dynamic threshold voltage transistor has conventionally been proposed in, for example, F. Assaderaghi et al., “A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation”, IEDM94, Ext. Abst. page 809, as a transistor operable at a low supply voltage. The dynamic threshold voltage transistor realizes a high driving power at a low voltage by reducing the effective threshold voltage when the transistor is ON.
FIG. 34
shows a structure of a conventional dynamic threshold voltage transistor.
FIG. 34
shows a dynamic threshold voltage transistor using an SOI substrate which is disclosed in U.S. Pat. No. 5,559,368 and Japanese Laid-Open Publication No. 6-85262.
FIG. 34
shows an NMOS structure, but a PMOS can also be realized by inverting the polarities.
FIG. 34A
is a cross-sectional view of the conventional dynamic threshold voltage transistor using an SOI substrate.
FIG. 34B
is a top view of the dynamic threshold voltage transistor, and
FIG. 34C
is a cross-sectional view thereof across a contact region of a gate electrode and a body. Reference numeral
1000
represents a silicon substrate, reference numeral
1001
represents a buried oxide layer, reference numeral
1002
represents a source region, reference numeral
1003
represents a p-type silicon layer, reference numeral
1004
represents a drain region, reference numeral
1005
represents a gate insulating layer, reference numeral
1006
represents a gate electrode, reference numeral
1007
represents a p-type diffusion layer, and reference numeral
1008
represents a metal line.
The SOI substrate is used, and the gate electrode
1006
and the p-type silicon layer
1003
are locally shortcircuited via the p-type diffusion layer
1007
and the oversized metal line
1008
. When a gate bias is applied to such a structure in which the gate electrode
1006
and the p-type silicon layer
1003
are shortcircuited, a forward bias is applied to an active region, the forward bias having an equal magnitude to that of the gate bias.
It should be noted that in this structure, the voltage to be applied to the gate electrode in order to restrict the standby current is restricted to 0.6 V or less. At or in the vicinity of 0.6 V, a lateral direction bipolar transistor is turned ON. Due to the restriction in the voltage, when the gate is OFF, the substrate is usually in the same bias state as that of the transistor, and when the gate is ON, the substrate is forwardly biased as the gate bias increases. In this manner, the threshold voltage is reduced. Therefore, the dynamic threshold voltage transistor has an equivalent leakage current to that of a general SOI transistor in the same channel state when the substrate bias (gate bias) is OFF. When the transistor is ON, a significant increase in the driving force is provided as the threshold voltage is reduced.
However, the above-described structure uses an SOI substrate. Accordingly, the body (p-type silicon layer as the channel region) has a very small thickness (50 nm to 200 nm) and thus obtains a very high resistance. Therefore, even when the gate electrode and body are shortcircuited by a contact region, it becomes more difficult to transfer the potential of the gate electrode to the body and the CR time constant becomes larger as the body is more distanced from the contact region. Thus, in terms of a transient operation, the effect of the dynamic threshold metal-oxide-silicon FET (DTMOSFET; hereinafter, referred to as the “DTMOS”) is restricted and the DTMOS device cannot operate at a high speed.
The source and drain regions have a great thickness and thus obtains a high resistance. It is effective to salicide the source and drain regions (self-aligned saliciding) using a refractory metal material in order to avoid the high resistance of the source and drain regions. However, it is difficult to salicide the source and drain regions which are formed of a very thin silicon layer on the oxide layer. In order to solve the problems of the DTMOS device using the SOI substrate, the present inventors proposed a dynamic threshold voltage transistor using a bulk silicon substrate (Japanese Laid-Open publication No. 10-22462). As shown in
FIG. 35
, the dynamic threshold voltage transistor using a bulk silicon substrate includes a MOSFET provided on a bulk silicon substrate
0301
. The MOSFET includes a deep well
0302
provided on the bulk silicon substrate
0301
, a shallow well
0303
having an opposite conductivity type to that of the deep well
0302
provided in the deep well
0302
, and source and drain regions
0307
of a conductivity type opposite to that of the shallow well
0303
(namely, the same conductivity type as that of the deep well
0302
) which are provided in the shallow well
0303
. A gate electrode
0306
of the MOSFET has a feature of being electrically connected to the shallow well
0303
. At least the shallow well
0303
is electrically isolated from a shallow well
03031
included in an adjacent transistor by a groove-type device isolation region
0304
. Reference numeral
0305
represents a gate oxide layer, reference numeral
0308
represents an interlevel isolating layer, and reference numeral
0309
represents a contact hole.
The structure shown in
FIG. 35
solves the problem of the increase in the resistance of the body of a DTMOS using an SOI substrate. However, when a bulk substrate is used, unlike the case of the SOI substrate, the planar size of the junction of the source and drain regions and the shallow well region increases, which accompanies an increase in the parasitic capacitance. The power consumption P is expressed by P=C×V
2
×f where V is the supply voltage, C is the capacitance of the circuit including the parasitic capacitance, and f is the operating frequency. In other words, it is important to reduce the supply voltage, and also to reduce the capacitance, in order to lower the power consumption. As compared to the usual MOSFET having a constant potential in the well region, the DTMOS having the structure shown in
FIG. 35
which shortcircuits the gate electrode and the body region or the well region is disadvantageous when the planar size of the junction of the source and drain regions and the well region is the same.
With reference to
FIGS. 36 and 37
, the parasitic capacitance will be described in detail.
FIG. 36
shows the state of a usual CMOS inverter having a fan-out of 1.
FIG. 37
shows the state of a CMOS inverter of a dynamic threshold voltage transistor having a fan-out of 1, in which the gate electrode and the well region are shortcircuited. In
FIGS. 36 and 37
, parasitic capacitances are indicated with “−” and “+”. As is easily appreciated from the comparison between
FIGS. 36 and 37
, the dynamic threshold voltage transistor shown in
FIG. 37
has a capacitance at the junction which is three times as high
Adachi Kouichiro
Iwata Hiroshi
Kakimoto Seizo
Nakano Masayuki
Lee Jr. Granvill D
Sharp Kabushiki Kaisha
Smith Matthew
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