Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-11-12
2001-02-20
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S233000, C438S299000
Reexamination Certificate
active
06190953
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a connector/connecting technique for semiconductor devices. More specifically, the invention relates to a connector/connecting technique for use in a semiconductor memory required to be highly integrated.
2. Description of the Background Art
Referring now to the accompanying drawings, the prior art will be described. In recent years, with the miniaturization of semiconductor chips, a local interconnect has beenused for connecting a gate electrode of a transistor to a diffusion layer. In particular, the local interconnect is effectively used for a semiconductor memory (SRAM) required to behighly integrated.
Referring to
FIGS. 1A through 1D
, a conventional method for forming a local interconnect and a contact will be described below.
First, as shown in
FIG. 1A
, a gate insulating film
3
and a gate electrode
4
are stacked on a semiconductor substrate
1
. Then, as shown in
FIG. 1B
, the gate electrode
4
is used as a mask to form diffusion layers
2
serving as sources or drains on the semiconductor substrate
1
using the ion implantation. Subsequently, an interlayer insulating film
7
of silicon dioxide is formed on the whole surface using the CVD method. The interlayer insulating film
7
is deposited so as to have an elevation higher than that of the gate electrode
4
. Then, as shown in
FIG. 1C
, the upper surface of the gate electrode
4
and the upper surfaces of one of the diffusion layers
2
are exposed toform an opening
7
A by means of the photo-etching. Thereafter, as shown in
FIG. 1D
, an electrode material
9
is deposited on the inner surface of the opening
7
A and the upper surface of the interlayer insulating film
7
using the sputtering or the like.
Then, as shown in
FIG. 2A
, the electrode material
9
on the interlayer insulating film
7
is removed by the CMP method. In the opening
7
A, the gate electrode
4
is electrically connected to one of the diffusion layers
2
to form a local interconnect LIC. Subsequently, as shown in
FIG. 2B
, an interlayer insulating film
8
of silicon dioxide is deposited on the whole surface by the CVD method. Thereafter, as shown in
FIG. 2C
, a contact hole
10
A is formed in the interlayer insulating films
7
and
8
so as to reach the diffusion layer
2
by means of the photo-etching. Subsequently, an electrode material
10
is embedded in the contact hole
10
A, and an upper layer wiring
11
is formed thereon. By these steps, the local interconnect LIC and a contact CT are formed.
In a case where a local interconnect LIC and a contact CT are formed by the above described conventional method, the contact CT is formed (see
FIGS. 2B through 2C
) after the local interconnect LIC is formed (see FIGS.
1
A through
2
A). That is, the local interconnect structure and the contact are separately produced. Therefore, there is a problem in that the number of steps is high to complicate the manufacturing method and to increase the costs.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a semiconductor device and a method for producing the same, which can prevent the increase of the number of steps of forming a local interconnect structure and a contact and which can provide simplified steps.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a semiconductor device comprises: a semiconductor substrate; a field oxide film formed in the semiconductor substrate, the field oxide film having element forming regions on both sides thereof; a pair of MOS transistors formed in the element forming regions on both sides of the field oxide film, each of the MOS transistors having a gate oxide film, a gate electrode and a pair of source/drain regions; an interlayer insulating film covering the semiconductor substrate, the field oxide film and the MOS transistors; a local interconnect formed by embedding a conductive material in a first opening formed in the interlayer insulating film, the first opening being arranged above the field oxide film and having a greater width than the field oxide film, an inner one of the pair of source/drain regions of each of the pair of MOS transistors being exposed to the first opening, the inner one of the pair of source/drain regions of one of the pair of MOS transistors being electrically connected to the inner one of the pair of source/drain regions of the other of the pair of MOS transistors by means of the local interconnect; and a pair of buried contacts formed by embedding a pair of conductive materials in a pair of second openings formed in the interlayer insulating film, the pair of second openings being arranged above an outer one of the pair of source/drain regions of each of the pair of MOS transistors, the outer one of the pair of source/drain regions being exposed to the second openings.
According to another aspect of the present invention, a semiconductor device comprises: a semiconductor substrate; a MOS transistor formed on the semiconductor substrate, the MOS transistor having a gate oxide film, a gate electrode and a pair of source/drain regions; an interlayer insulating film covering the semiconductor substrate and the MOS transistor; a local interconnect formed by embedding a conductive material in a first opening formed in the interlayer insulating film, part or all of the gate electrode and all or part of one of the source/drain regions being exposed to the first opening, the gate electrode being electrically connected to one of the source/drain regions by means of the local interconnect; a buried contact formed by forming a second opening in the interlayer insulating film, the surface of the semiconductor substrate being exposed to the second opening; a second insulating film covering the interlayer insulating film, the local interconnect and the buried contact so that the interlayer insulating film, the local interconnect and the buried contact are flush with each other; and a wiring formed by embedding a wiring material in a wiring embedding groove formed in the second insulating film, the buried contact being exposed to the groove.
According to further aspect of the present invention, a method for producing a semiconductor device, comprises the steps of: forming a MOS transistor on a semiconductor substrate so that the MOS transistor has a gate insulating film, a gate electrode and a pair of source/drain regions; forming an interlayer insulating film thereon; forming first and second openings in the interlayer insulating film so that both of the gate electrode and one of the source/drain regions are exposed by the first opening and the surface of the semiconductor substrate is exposed by the second opening; embedding conductive materials in the first and second openings of the interlayer insulating film; performing the etch back of the conductive materials so that the conductive materials in the first and second openings are level with the interlayer insulating film; forming a second insulating film thereon; forming a wiring embedding groove in the second insulating film; and embedding a wiring material in the groove.
REFERENCES:
patent: 4945070 (1990-07-01), Hsu
patent: 5151376 (1992-09-01), Spinner, III
patent: 5158910 (1992-10-01), Cooper et al.
patent: 5516726 (1996-05-01), Kim et al.
patent: 5693975 (1997-12-01), Lien
patent: 5940735 (1999-08-01), Mehta et al.
Igarashi Wataru
Naruke Yasuo
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshibia
Picardat Kevin M.
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