Semiconductor device and method for manufacturing thereof

Semiconductor device manufacturing: process – Chemical etching – Combined with coating step

Reexamination Certificate

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C438S696000, C438S697000, C438S698000, C438S700000

Reexamination Certificate

active

06916743

ABSTRACT:
A semiconductor device manufacturing method that enables accurate recognition of an alignment mark and optimal formation of a buried wiring. The method includes depositing an insulation film above a semiconductor device, and then etching the insulation film to form a buried wiring hole and an alignment mark pit in the insulation film. Subsequently, a conductive film is deposited on the surface of the insulation film that includes the buried wiring hole and the alignment mark pit. The conductive film is deposited so that it is less than the depth of the alignment mark pit and less than half of a minimum opening width of the alignment mark pit.

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Japanese Patent Office Communication dated Apr. 20, 2004 for Japanese Application No. 2001-219173.
Japanese Patent Office Communication dated Apr. 20, 2004 for Japanese Application No. 2001-219173 and English language translation.
European Search Report dated Nov. 7, 2002.

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