Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2005-07-12
2005-07-12
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S696000, C438S697000, C438S698000, C438S700000
Reexamination Certificate
active
06916743
ABSTRACT:
A semiconductor device manufacturing method that enables accurate recognition of an alignment mark and optimal formation of a buried wiring. The method includes depositing an insulation film above a semiconductor device, and then etching the insulation film to form a buried wiring hole and an alignment mark pit in the insulation film. Subsequently, a conductive film is deposited on the surface of the insulation film that includes the buried wiring hole and the alignment mark pit. The conductive film is deposited so that it is less than the depth of the alignment mark pit and less than half of a minimum opening width of the alignment mark pit.
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Okayama Yoshio
Yamashita Tomio
Norton Nadine G.
Sanyo Electric Co,. Ltd.
Tran Binh X.
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