Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-11-06
2004-03-30
Chen, Jack (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S003000, C438S250000, C438S256000, C438S393000
Reexamination Certificate
active
06713344
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same; and, more particularly, to a semiconductor device and a manufacturing method capable of preventing diffusion of impurities such as hydrogen ions or moisture produced during a process using plasma.
DESCRIPTION OF RELATED ARTS
As a semiconductor device manufacturing technology has been rapidly developed, it is a trend in today to produce a semiconductor device with high degrees of capacity and function. Therefore, it is required to integrate more devices in a limited area, and this factor results in a continuous research and development to form a pattern on a semiconductor substrate to be highly micronized and integrated.
Plasma dry etching technique or plasma enhanced chemical vapor deposition technique is employed to fabricate a semiconductor device with high degrees of micronization and integration. In case of the plasma dry etching technique, a reactant gas is activated to be changed into a plasma state, and then positive ions or radicals of the plasma etch a target layer.
According to different types of plasma generation, a chamber in which a plasma process proceeds is classified into Reactive Ion Etching (RIE), Magnetically Enhanced Reactive Ion Etching (MERIE), Chemical Downstream Etching (CDE), Electron Cyclotron Resonance (ECR), and Transformer Coupled Plasma (TCP) and so on. Also, according to different types of power supply, the chamber can be also classified as Capacitive Coupled Plasma (CCP) and Inductive Coupled Plasma (ICP).
The CCP type forms an electric field by selectively supplying a high frequency power to a plurality of electrodes equipped inside a process chamber so as to change a reactant gas into a plasma state. The ICP type changes a reactant gas into a plasma state through the use of a magnetic and an electric fields generated by selectively supplying a high frequency power to a plurality of coils wound outside a process chamber and a plurality of electrodes equipped inside the process chamber.
In an etching and a deposition processes that use plasma, it is inevitable to use gases including impurities in high energy states, e.g., hydrogen ions, moisture, electrons or argon ions, and plasma containing these impurities gets penetrated inside a device such as a capacitor and the like, causing properties of the device to be degraded.
With reference to
FIG. 1
, there are described a method for manufacturing a capacitor of a semiconductor device.
Referring to
FIG. 1
, a first inter-layer insulation layer
13
is formed on a semiconductor substrate
10
on which a device isolation layer
11
and a transistor including a gate pattern
12
are formed.
Next, a capacitor including a bottom electrode
15
, dielectric layer
16
and a top electrode
17
is formed on the first inter-layer insulation layer
13
. Reference numeral
14
denotes an adhesion layer for improving adhesion between the first inter-layer insulation layer
13
and the bottom electrode
15
.
A second inter-layer insulation layer
18
is then formed over the semiconductor substrate
10
after forming the capacitor. Subsequently, the second inter-layer insulation layer
18
is selectively etched to expose the top electrode
17
. Then, a TiN diffusion barrier
19
contacted to the top electrode
17
is formed.
A metal line is formed for connecting the capacitor and an active area of the transistor. The metal line includes sequentially formed layers of a Ti layer
20
, a TiN layer
21
and a metal layer
22
.
As illustrated in
FIG. 1
, the TiN diffusion barrier
19
is formed on between the top electrode
17
and the Ti layer
20
. The TiN diffusion barrier
19
functions to prevent degradation of capacitor properties, caused by a Ti penetration through a grain boundary of the top electrode
17
when the Ti layer
20
makes a direct contact to the top electrode
17
.
In a reactive ion etching (RIE) process, plasma is particularly used for patterning the TiN diffusion barrier
19
. However, impurities in high energy states contained in the plasma, e.g., hydrogen ions, moisture, electrons and argon ions and so forth, get penetrated into the capacitor, inducing degradation of the capacitor properties. These impurities are usually penetrated through an interface between the second inter-layer insulation layer
18
and the TiN diffusion barrier
19
.
Hence, it is important to prevent impurities from penetrating into the capacitor to reduce degradation of the capacitor properties. It is, therefore, required to develop a plasma process and a subsequent process in which impurities such as hydrogen ions or moisture are not produced during these processes. However, there still present technical difficulties and cost problems to develop the above mentioned processes.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a semiconductor device and a manufacturing method capable of preventing impurities with high energy states contained in plasma from penetrating into a capacitor, and thereby, ultimately maintaining properties of the semiconductor device.
In accordance with an aspect of the present invention, there is provided a semiconductor device, including: a capacitor formed on a top portion of a semiconductor substrate, wherein the capacitor includes a bottom electrode, a dielectric layer and a top electrode; an Iridium (Ir) capping layer formed on the top electrode of the capacitor; an inter-layer insulation layer for covering the capacitor and the Ir capping layer; a Ti layer for preventing plasma that contains impurities from penetrating into the capacitor through a contact hole, wherein the Ti layer is contacted with the inter-layer insulation layer exposed on lateral sides of the contact hole and the Ir capping layer exposed on a lower side of the contact hole; and a metal line formed on the Ti layer.
In accordance with another aspect of the present invention, there is also provided a method for manufacturing a semiconductor device, including the steps of: forming a capacitor including a bottom electrode, a dielectric layer and a top electrode on a semiconductor device; forming an Ir capping layer on the top electrode of the capacitor; forming an inter-layer insulation layer covering the Ir capping layer and the capacitor; forming a contact hole by selectively etching the inter-layer insulation layer, wherein the inter-layer insulation layer is exposed at the lateral side of the contact hole and the Ir capping layer is exposed at the bottom surface of the contact hole; forming a Ti layer for preventing plasma containing impurities from penetrating into the capacitor, wherein the Ti layer is contacted to the Ir capping layer at the bottom surface of the contact hole and the inter-layer insulation layer at the lateral side of the contact hole; and proceeding a process using the plasma.
In accordance with still another aspect of the present invention, there is also provided a method for manufacturing a semiconductor device, including the steps of: preparing a semiconductor substrate on which a transistor including a gate insulation layer, a gate electrode and junctions are already formed; forming a first inter-layer insulation layer on the semiconductor substrate; forming a capacitor including a bottom electrode, a dielectric layer and a top electrode on the first inter-layer insulation layer; forming an Ir capping layer on the top electrode of the capacitor; forming a second inter-layer insulation layer on the semiconductor substrate; forming a first contact hole by selectively etching the second inter-layer insulation layer, wherein the Ir capping layer is exposed at the bottom surface of the first contact hole and the second inter-layer insulation layer is exposed at the lateral side of the first contact hole, and forming a second contact hole by selectively etching the first and the second inter-layer insulation layers, wherein the junction of the transistor is exposed; forming a Ti layer for preventing plasma with impurities from penetrating i
Chen Jack
Hynix / Semiconductor Inc.
Jacobson & Holman PLLC
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