Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-10-23
2004-03-02
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06699758
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a technique for improvement in characteristics of an input protection circuit in an LSI.
2. Description of the Background Art
In a MOSFET, a well-known method for effectively enhancing a proof stress against variation in voltage amplitude of an input signal which is applied to a source/drain region is formation of a silicide protection. This method is, for example, to form an SiO
2
film over a gate electrode and side walls and then forming silicide on a surface portion of an n
+
-type layer uncovered with the SiO
2
film as shown in
FIG. 33
, thereby raising a resistance of the source/drain region near the gate electrode without forming silicide on the region.
In a MOS structure using SOI (Silicon On Insulator), however, since the SOI layer is very thin (e.g., its thickness is about 1000 Å), the SOI layer is etched in an etching to form the SiO
2
film for silicide protection. If the SOI layer is etched, too, part of the SOI layer becomes thin because of level difference and the silicide layer which should originally extend from a surface of the SOI layer to the inside thereof reaches an interface between the SOI layer and a buried oxide film, to disadvantageously cause a leakage current and remove the silicide film.
This will be discussed below with reference to cross-sectional step views of
FIGS. 29
to
35
.
In order to avoid silicification of the source/drain region near the gate electrode by covering the region with the SiO
2
film, usually, a series of steps shown in
FIGS. 29
to
33
are carried out. Specifically, a gate electrode and source/drain regions are formed as shown in
FIG. 29
, and an SiO
2
film is deposited as shown in FIG.
30
. Next, a resist is formed on a portion of the SiO
2
film which is to serve as the silicide protection portion as shown in
FIG. 31
, and a dry etching is performed to form an SiO
2
film to serve as the silicide protection portion. After that, the unnecessary resist is removed. Then, a silicide layer is formed as shown in FIG.
34
.
Since the Si layer as the SOI layer is very thin, about 1000 Å, the Si layer is also etched in the dry etching and as a result a level difference as shown in
FIG. 34
is created locally in a surface of the Si layer. In this condition, when silicide is formed on a prescribed uncovered portion of the source/drain region, the buried oxide film and a silicide layer come into contact as shown in FIG.
35
. Since the silicide layer weakly adheres to the buried oxide film in this condition, there is a possibility that the silicide layer may be removed depending on the strength of thermal stress applied in later steps. Further, even if the silicide layer is not removed, a leakage current may be produced between two silicide layers through the buried oxide film, and therefore there may arise an appreciable influence on characteristics of a transistor such as malfunction in a transistor operation.
Regarding this point, Japanese Patent Application Laid Open Gazette 64-20663 discloses that in a dry etching for forming a side wall of a gate electrode of a MOS transistor, an Si
3
N
4
film is formed as an etching stopper film in advance on a surface of a semiconductor layer to cover both sides of the gate electrode and a gate insulating film and then a side wall is so formed as to cover the Si
3
N
4
film. This prior art, however, which essentially suggests a side wall of double-layered structure consisting of the Si
3
N
4
film and the SiO
2
film, can not be an effective solution of the above problem.
SUMMARY OF THE INVENTION
The present invention is directed to a semiconductor device. According to a first aspect of the present invention, the semiconductor device comprises: an underlying layer; a semiconductor layer provided on a surface of the underlying layer; a gate insulating film provided on a first region in a flat surface of the semiconductor layer; a gate electrode provided on a surface of the gate insulating film; a side wall provided on second and third regions adjacent to the first region in the flat surface of the semiconductor layer, covering side surfaces of the gate insulating film and side surfaces of the gate electrode; a first insulating film provided on fourth and fifth regions adjacent to the second and third regions, respectively, in the flat surface of the semiconductor layer, on surfaces of the side walls and on a surface of the gate electrode; a second insulating film provided on a surface of the first insulating film, being different in material from the first insulating film; a first impurity layer of the first conductivity type extending from a center portion of the first region to the inside of the semiconductor layer; a second impurity layer of the second conductivity type adjacent to the first impurity layer, extending from one of peripheral portions of the first region, the second region, the fourth region, a sixth region externally adjacent to the fourth region to the inside of the semiconductor layer; a third impurity layer of the second conductivity type adjacent to the first impurity layer, extending from the other of the peripheral portions of the first region, the third region, the fifth region, a seventh region externally adjacent to the fifth region to the inside of the semiconductor layer; a first silicide layer provided on the sixth region and inside the second impurity layer located immediately below the sixth region, of which a bottom surface is located inside the second impurity layer; and a second silicide layer provided on the seventh region and inside the third impurity layer located immediately below the seventh region, of which a bottom surface is located inside the third impurity layer.
According to a second aspect of the present invention, the semiconductor device of the first aspect further comprises: a third insulating film provided on a surface of the second insulating film.
According to a third aspect of the present invention, in the semiconductor device of the second aspect, the first insulating film and the third insulating film are of the same material.
According to a fourth aspect of the present invention, in the semiconductor device of the first aspect, the first insulating film is an SiO
2
film.
According to a fifth aspect of the present invention, in the semiconductor device of the first aspect, the first insulating film is an Si
3
N
4
film.
According to a sixth aspect of the present invention, the semiconductor device comprises: a semiconductor layer; a gate insulating film formed on a surface of the semiconductor layer; a gate electrode formed on a surface of the gate insulating film; a side wall formed on the surface of the semiconductor layer to cover side surfaces of the gate insulating film and side surfaces of the gate electrode; and first and second insulating layers formed on the surface of the semiconductor layer in this order by dry etching to cover surfaces of the side walls and a surface of the gate electrode, and in the semiconductor device, an etching rate of the second insulating layer is set larger than that of the first insulating layer in the dry etching.
According to a seventh aspect of the present invention, in the semiconductor device of the sixth aspect, a portion of the first insulating layer uncovered with the second insulating layer after the dry etching is removed by wet etching.
According to an eighth aspect of the present invention, in the semiconductor device of the seventh aspect, the first insulating layer comprises first and second insulating films of different materials, and the etching rate of the second insulating layer is set larger than that of the second insulating film adjacent to the second insulating layer.
The present invention is also directed to a method for manufacturing a semiconductor device. According to a ninth aspect of the present invention, the method comprises the steps of: (a) providing a semiconductor
Hirano Yuuichi
Maegawa Shigeto
Yamaguchi Yasuo
Chaudhuri Olik
Kebede Brook
Mitsubishi Denki & Kabushiki Kaisha
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