Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-02-15
2003-09-09
Le, Vu A. (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06617219
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of lowering and/or reducing the Miller capacitance at the edges of a structure such as a gate structure of an MOS transistor.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the FET, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
However, reducing the channel length of a transistor also increases “short-channel” effects, almost by definition, as well as “edge effects” that are relatively unimportant in long channel transistors. Short-channel effects include, among other things, an increased drain-source leakage current when the transistor is supposed to be switched “off,” believed to be due to an enlarged depletion region relative to the shorter channel length. One of the edge effects that may influence transistor performance is known as Miller capacitance. The Miller capacitance is an overlap capacitance that arises because the conductive doped-polycrystalline silicon (doped-poly) gate almost invariably overlaps with a conductive portion of either the more heavily-doped source/drain regions or the less heavily-doped source/drain extension (SDE) regions, if present, of a conventional metal oxide semiconductor field effect transistor (MOSFET or MOS transistor).
As shown in
FIG. 1
, for example, a conventional MOS transistor
100
may be formed on a semiconducting substrate
105
, such as doped-silicon. The MOS transistor
100
may have an N
+
-doped-poly (P
+
-doped-poly) gate
110
formed above a gate oxide
115
formed above the semiconducting substrate
105
. The N
+
-doped-poly (P
+
-doped-poly) gate
110
and the gate oxide
115
may be separated from N
+
-doped (P
+
-doped) source/drain regions
120
of the MOS transistor
100
by dielectric spacers
125
. The dielectric spacers
125
may be formed above N
−
-doped (P
−
-doped) source/drain extension (SDE) regions
130
. As shown in
FIG. 1
, shallow trench isolation (STI) regions
140
may be provided to isolate the MOS transistor
100
electrically from neighboring semiconductor devices such as other MOS transistors (not shown).
The N
−
-doped (P
−
-doped) SDE regions
130
are typically provided to reduce the magnitude of the maximum channel electric field found close to the N
+
-doped (P
+
-doped) source/drain regions
120
of the MOS transistor
100
, and, thereby, to reduce the associated hot-carrier effects. The lower (or lighter) doping of the N
−
-doped (P
−
-doped) SDE regions
130
, relative to the N
+
-doped (P
+
-doped) source/drain regions
120
of the MOS transistor
100
(lower or lighter by at least a factor of two or three), reduces the magnitude of the maximum channel electric field found close to the N
+
-doped (P
+
-doped) source/drain regions
120
of the MOS transistor
100
, but increases the source-to-drain resistances of the N
−
-doped (P
−
-doped) SDE regions
130
.
As shown in
FIG. 1
, typically there are overlap regions
135
(indicated in phantom) where the edges of the N
+
-doped-poly (P
+
-doped-poly) gate
110
overlap with the edges of the N
−
-doped (P
−
-doped) SDE regions
130
. The typical amount of overlap &Dgr; in each of the overlap regions
135
, as shown in
FIG. 1
, may be about 200 Å, for example. These overlap regions
135
give rise to the Miller capacitance. As the overall dimensions of the MOS transistor
100
are reduced, the Miller capacitance becomes more of a dominant factor, particularly affecting the switching speed of the MOS transistor
100
. For example, when the MOS transistor
100
is in an “off” state, there may be some residual charge stored in the overlap regions
135
primarily due to the Miller capacitance. This “Miller charge” must be discharged before the MOS transistor
100
may be switched from the “off” state to an “on” state, slowing down the switching speed. Similarly, the Miller capacitance in the overlap regions
135
must be charged up again with the “Miller charge” after the MOS transistor
100
is switched from the “on” state to the “off” state, further slowing down the switching speed.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method is provided, the method including forming a gate dielectric above a surface of the substrate, forming the conductive gate structure above the gate dielectric, the conductive gate structure having an edge region, and forming a source/drain extension (SDE) adjacent the conductive gate structure. The method also includes forming a dopant-depleted-SDE region in the substrate under the edge region of the conductive gate structure.
In another aspect of the present invention, an MOS transistor having a reduced Miller capacitance is provided, the MOS transistor formed by a method including forming a gate dielectric above a surface of the substrate, forming a conductive gate structure above the gate dielectric, the conductive gate structure having an edge region, and forming a source/drain extension (SDE) adjacent the conductive gate structure. The method also includes forming a dopant-depleted-SDE region in the substrate under the edge region of the conductive gate structure.
In yet another aspect of the present invention, an MOS transistor is provided, the MOS transistor including a gate dielectric above a surface of a substrate, a doped-poly gate structure above the gate dielectric, the conductive gate structure having an edge and an edge region, and a source/drain extension (SDE) adjacent the conductive gate structure. The MOS transistor also includes a dopant-depleted-SDE region in the substrate under the edge region of the conductive gate structure.
REFERENCES:
patent: 5320974 (1994-06-01), Hori et al.
patent: 5360751 (1994-11-01), Lee
patent: 5532175 (1996-07-01), Racanelli et al.
patent: 5593907 (1997-01-01), Anjum et al.
patent: 5917219 (1999-06-01), Nandakumar et al.
patent: 6020244 (2000-02-01), Thompson et al.
patent: 6083794 (2000-07-01), Hook et al.
patent: 6103562 (2000-08-01), Son et al.
patent: 6124616 (2000-09-01), Dennison et al.
patent: 6194748 (2001-02-01), Yu
patent: 6255152 (2001-07-01), Chen
patent: 6255175 (2001-07-01), Yu
patent: 6358805 (2002-03-01), Son et al.
patent: 6372587 (2002-04-01), Cheek et al.
High-performance sub-0.1- mu m CMOS with low-resistance T-shaped gates fabricated by selective CVD-W.. 1995 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.95CH35781) Tokyo, Japan: Japan Soc. Appl. Phys, 1995. p.115-16.*
A device design study of 0.25 mu m gate length CMOS for 1 V low power applications.. 1995 IEEE Symposium on Low Power Electronics. Dig
Aminpur Massud
Duane Michael P.
Luning Scott D.
Wu David D.
Advanced Micro Devices , Inc.
Le Vu A.
Luhrs Michael K.
Williams Morgan & Amerson
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