Semiconductor device and method for initializing interface...

Details Semiconductor device and method for initializing interface... Semiconductor device and method for initializing interface...

2002-10-07

2004-05-25

Fleming, Fritz (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Peripheral configuration

C710S022000, C710S301000

Reexamination Certificate

active

06742056

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device and a method for initializing an interface card using a serial electrically erasable and programmable read only memory (EEPROM).
2. Description of the Related Art
In current semiconductor systems, it is common for a PCI bus or cardbus PC card to be used as an interface between circuits In general, the PCI bus is used as an interface to transmit data at high speeds, whereas the cardbus PC card is an interface that adopts a PCI bus structure due to restrictions on the transmission bandwidth of a conventional personal computer memory card international association (PCMCIA) card.
Most PCI cards or cardbus PC cards simply process data using only a digital signal processor without a central processing unit (CPU). Since there is a need for data to be processed at higher speeds and managed more effectively, system-on-a-chip (SOC)-type systems that include CPUs have been developed.
In the case of a PCI system, a plurality of PCI cards are connected to a PCI bus. A HOST/PCI bridge is installed between the CPU of a host system and the PCI bus, and a plurality of PCI cards may be connected to the PCI bus. A cardbus PC card system may have a connection structure similar to that of the PCI system.
An SOC-type PCI interface chip including a CPU may be used in a PCI card. In the PCI card, a configuration register of a PCI interface unit must be initialized to a predetermined state. A configuration register of the PCI card must also be initialized to a predetermined state.
FIG. 1
is a register map showing the structure of a configuration register of a PCI card. Referring to
FIG. 1
, the bit positions of registers are marked along the X-axis, and the register addresses are expressed as hexadecimal numbers along the Y-axis. Registers for classifying PCI cards are shown in FIG.
1
. Specifically, device identification (ID), vendor ID, class code, revision code, subsystem ID, and subsystem vendor ID are data required in order to classify and identify PCI cards in a host CPU of a personal computer system or in order to perform a plug-and-play operation. The vendor ID is used for an interface number that is used to identify the manufacturer of an interface system on chip mounted on a PCI card, and the device ID is used for an ID number of a chip given by the manufacturer, the class code is used to identify the type of chip mounted on a PCI card, and the revision code identifies the version of a chip. The subsystem vendor ID identifies the manufacturer of a PCI card, on which a chip will be mounted, and the subsystem ID contains the ID number of a PCI card given by the manufacturer. The device ID and the vendor ID are data specific to a PCI interface chip and are set by the manufacture of the chip. However, since there are various PCI cards manufactured by different manufacturers, on which chips will be mounted, it is impossible for the chip manufacturers to fix the class code, revision code, subsystem Id, and subsystem vendor ID of a PCI card without using an external memory. A cardbus PC card includes a configuration register having substantially the same structure as that of a configuration register of a PCI card.
Hereinafter, the class code, revision code, subsystem ID, and subsystem vendor of a PCI card are referred to as the initial data of a PCI card.
Card information structure (CIS) information in a cardbus PC card system displays predetermined data concerning a cardbus PC card, which are fixed data and thus cannot be changed during operation of the cardbus PC card.
A central processing unit (CPU) host reads data stored in one of the registers shown in
FIG. 1
in order to read CIS information stored in a cardbus PC card. The CPU host than analyzes the data and identifies the part of the register in which the CIS information is located. Next, the host CPU reads the CIS information from the register and allows the cardbus PC card to operate. However, in the case when the CIS information is not located at a desired position, it is impossible to determine which kind of card is connected to a cardbus and allow the card to appropriately operate. Accordingly, it becomes necessary to move the CIS information from an original location where the CIS information is originally stored, to another location where the time taken to access the CIS information can be reduced.
FIG. 2
is a block diagram of a conventional semiconductor device for initializing a PCI card or a cardbus PC card. Referring to
FIG. 2
, a conventional semiconductor device
200
is a chip
200
installed in a PCI card or a cardbus PC card. The chip
200
includes a CPU
210
connected to a system bus, a memory controller
220
, and an interface
230
.
In the conventional systems, in order to initialize a PCI card, the CPU
210
reads initialization information INIFORM from an external read only memory (ROM)
240
using the memory controller
220
after the reset operation of the PCI card is completed, and stores the initialization information in a predetermined register of the interface
230
, thus initializing the interface
230
. The initialization information is stored in the ROM
240
as data or as a program. Since the ROM
240
is necessary for initializing the PCI card, it is difficult to modify a program concerning the initialization information stored in the ROM
240
.
In the case of a cardbus PC card, like the PCI card described above, the CPU
210
reads the initialization information from the ROM
240
using the memory controller
220
after the reset operation of the cardbus PC card is completed and stores the initialization information in a predetermined register of an interface
230
, thus initializing the interface
230
. Since the ROM
240
is necessary for initializing the cardbus PC card, like the PCI card, it is also difficult to modify a program that includes the initialization information stored in the ROM
240
. In addition, CIS information must also be stored in the cardbus PC card, unlike the PCI card.
FIG. 3
is a block diagram of a conventional semiconductor device for initializing a PCI card or a cardbus PC card. Referring to
FIG. 3
, a conventional semiconductor device
300
is a chip
300
installed in a PCI card or a cardbus PC card. The chip
300
includes a memory controller
310
connected to a bus system and an interface
320
. The interface
320
includes a serial electrically erasable and programmable read only memory (EEPROM) interface
330
.
The semiconductor device
300
shown in
FIG. 3
, unlike the semiconductor device
200
shown in
FIG. 2
, uses only a serial EEPROM
340
, in which only the initialization information necessary to initialize the interface
320
is stored, instead of the external ROM
240
shown in FIG.
2
. In other words, after the reset operation of a PCI card or a cardbus PC card is completed, the serial EEPROM interface
330
in the interface
320
automatically reads initialization information INIFORM of the serial EEPROM
340
and stores the initialization information in a predetermined register, thus initializing the interface
320
. In this manner, it is not necessary for the CPU to be in the chip
300
in a PCI card or a cardbus PC card, since a device driver of a host system downloads a program for operating the PCI card or the cardbus PC card from a volatile memory (not shown), such as a SRAM, which is located outside the chip
300
, via a bus system installed in the chip
300
, thus operating the PCI card or the cardbus PC card.
In the case of operating the PCI card or the cardbus PC card using a downloaded program, the initialization information of the PCI card or the cardbus PC card is stored in the serial EEPROM
340
and is automatically read by the serial EEPROM interface
330
in the interface
320
after resetting the PCI card or the cardbus PC card.
In the above-described method, the PCI card or the cardbus PC card is generally initialized using the serial EEPROM interface
330
installed in the

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