Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-07
2002-05-28
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000
Reexamination Certificate
active
06395598
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device such as MIS transistor and a method for fabricating the same.
2. Description of the Related Art
A LOCOS structure has been used widely to electrically isolate devices included in a semiconductor integrated circuit from each other. But this structure is not suited for isolating devices in a VLSI, because it is almost impossible to avoid a so-called “bird's beak” problem when the LOCOS structure is adopted. Thus, an STI (shallow trench isolation) structure was proposed as alternate isolation structure substituting for the LOCOS. The STI structure is formed by filling in relatively shallow trenches, which have been provided to a depth of about 0.2 to about 0.6 &mgr;m in respective regions of a silicon substrate for electrical isolation purposes, with an SiO
2
film.
The STI structure is effectively applicable instead of the LOCOS structure when the area of the source/drain regions is small, i.e., when the distance between an edge of the gate and that of the nearest part of the isolation region is short. Specifically, significant effects are attainable if the STI structure is applied to a semiconductor integrated circuit to electrically isolate very small sized transistors, in which the distance between the gate edge and isolation region edge is about 0.7 &mgr;m or less.
Hereinafter, a method for fabricating a conventional semiconductor device with the STI structure will be described with reference to FIGS.
1
(
a
) through
1
(
d
).
First, a structure shown in FIG.
1
(
a
) is formed. This structure includes: a trench
10
that has been formed in an isolation region of a silicon substrate
1
; and an SiO
2
film
11
that has been deposited to fill in the trench
10
. The trench
10
and the SiO
2
film
11
together form an STI structure.
A region interposed between a pair of isolation regions functions as active region. The structure shown in FIG.
1
(
a
) includes: a gate insulating film
2
formed in the active region; a gate electrode
3
formed over the gate insulating film
2
; and source/drain regions
4
formed in the upper surface regions of the silicon substrate
1
. And an MIS transistor is made up of these components
1
,
2
,
3
and
4
. In FIG.
1
(
a
) , an SiO
2
film
5
a
is deposited to cover both the active and isolation regions alike.
Next, as shown in FIG.
1
(
b
), the SiO
2
film
5
a
is etched back such that part of the SiO
2
film
5
a
is left on the side faces of the gate electrode
3
, thereby forming a sidewall spacer
5
b.
Thereafter, dopant ions are implanted into the source/drain regions
4
using the gate electrode
3
and sidewall spacer
5
b
as mask. As a result, parts of the source/drain regions
4
are heavily doped, while other parts of the source/drain regions
4
located under the sidewall spacer
5
b
function as lightly doped drain (LDD) regions.
When the SiO
2
film
5
a
is etched back, however, the uppermost part of the STI structure, i.e., the uppermost part of the Sio
2
film
11
within the trench
10
, is also etched un-intentionally. As a result, a level difference is caused between the upper surface of the active region and that of the SiO
2
film
11
in the isolation region. Specifically, the upper surface of the SiO
2
film
11
falls to a level lower than that of the active region. This level difference is estimated to be about 20 to about 100 nm.
Then, as shown in FIG.
1
(
c
), these structures are covered with an interlevel dielectric film
6
and predetermined part of the interlevel dielectric film
6
is etched away, thereby forming a contact hole
12
in that part. As a result of this etching process step, the upper part of the SiO
2
film
11
, which is exposed inside the contact hole
12
crossing both the active and isolation regions, is further etched away to increase the level difference up to about 50 to about 200 nm.
Recently, the junction depth of the source/drain regions
4
tends to be decreasing year after year. In a semiconductor device with the STI structure, where a great number of components are integrated, the junction depth of the source/drain regions
4
is now about 30 to about 150 nm, which is shallower than the level difference. Accordingly, in the process step shown in FIG.
1
(
c
), the pn junction portion between the source/drain regions
4
and the silicon substrate
1
is exposed on a side of the stepped portion.
Subsequently, as shown in FIG.
1
(
d
), the contact hole
12
of the interlevel dielectric film
6
is filled in with a metal plug
13
of tungsten, for example. The metal plug
13
is provided to electrically connect an upper-level interconnection layer (not shown) formed on the interlevel dielectric film
6
to the source/drain regions
4
.
As shown in FIG.
1
(
d
), part of the pn junction portion between the source/drain regions
4
and the silicon substrate
1
is in direct contact with the metal plug
13
. As a result, a large amount of leakage current flows through a path indicated schematically by the arrow in FIG.
1
(
d
).
FIGS.
2
(
a
) and
2
(
b
) illustrate a situation where relatively narrow contact holes
12
are formed over relatively wide source/drain regions
4
and filled in with metal plugs
13
. Such a structure is applicable to a semiconductor device where a smaller number of components are integrated together. In this case, the metal plugs
13
are in contact with only the upper surface of the source/drain regions
4
, not with the pn junction portion between the source/drain regions
4
and the silicon substrate
1
. Thus, no leakage current flows through the metal plugs
13
. If the distance Z shown in FIG.
2
(
b
) is about 0.8 &mgr;m or more, then it is relatively easy to form the metal plugs
13
not reaching the nearest isolation regions filled in with the SiO
2
film
11
. But when the number of components integrated increases so much as to make the distance Z less than 0.8, &mgr;m, it is difficult to form the metal plugs
13
not reaching the nearest isolation regions.
Also, in the structure shown in FIGS.
2
(
a
) and
2
(
b
), even when the interlevel dielectric film
6
is etched to form the contact holes, the SiO
2
film
11
inside the trenches is not etched, either. Furthermore, since the junction depth X of the source/drain regions
4
is relatively large in the prior art structure, the level difference Y between the upper surface of the active region
20
and that of the SiO
2
film
11
is smaller than the junction depth X. Thus, even if the contact hole has shifted so much as to make the metal plug
13
cross the boundary between the active and isolation regions, the pn junction portion between the source/drain regions
4
and the silicon substrate
1
does not come into contact with the metal plug
13
. Accordingly, the leakage current path such as that shown in FIG.
1
(
d
) was not formed in the prior art structure.
It is now clear, however, that the current leakage will be almost always caused through that path when the fabricating process shown in FIGS.
1
(
a
) through
1
(
d
) has to be adopted in the near future to catch up the everlasting downsizing trend of semiconductor devices.
SUMMARY OF THE INVENTION
An object of the present invention is eliminating current leakage, which usually results from a level difference between source/drain regions and an STI structure when a contact hole for connecting the source/drain regions to an interconnection layer crosses the boundary therebetween.
A semiconductor device according to the present invention includes: a semiconductor substrate including an active region and an isolation region; an MIS transistor formed in the active region; a trench isolation structure formed in the isolation region; an insulating film covering both the MIS transistor and the trench isolation structure; an interlevel dielectric film, which is formed on the insulating film and provided with an opening reaching part of source/drain doped regions of the MIS transistor and part of the trench isolation
Hirai Takehiro
Kamada Hiroyuki
Kawahara Hiroyuki
Nakao Ichiro
Nelms David
Nhu David
Nixon & Peabody LLP
Robinson Eric J.
LandOfFree
Semiconductor device and method for fabricating the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method for fabricating the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method for fabricating the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2874115