Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-15
2002-09-24
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S309000
Reexamination Certificate
active
06455364
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the semiconductor device, and more particularly, relates to a hetero bipolar transistor, a Bi-CMOS device including the hetero bipolar transistor, and method for fabricating such devices.
2. Description of Related Art
In recent years, the development of hetero bipolar transistors (HBT) is in progress at rapid paces. The HBT, which is a bipolar transistor formed on a silicon substrate constituting a heterojunction structure such as Si/SiGe and Si/SiC together with the silicon substrate, is expected to be able to exhibit further improved conductivity characteristics for realizing operation in a higher-frequency range. The HBT is formed by growing a SiGe layer on a Si substrate by epitaxy to form a Si/SiGe heterojunction structure, for example. This heterojunction structure can be utilized to realize a transistor capable of operating in a high-frequency range. Such operation was only possible by transistors using a compound semiconductor substrate such as GaAs. The HBT is composed of materials having good compatibility for general silicon processes, such as the Si substrate and the SiGe layer, thereby providing great advantages of realizing a large scale of integration and low cost. In particular, by integrating such HBT and MOS transistors (MOSFETs) on a common Si substrate, a high-performance Bi-CMOS device can be realized. Such a Bi-COMS device has a great potential as a system LSI applicable in the field of telecommunications.
As a bipolar transistor constituting a Bi-CMOS device, hetero bipolar transistors having a heterojunction structure such as Si/Si
1−x
Ge
x
and Si/Si
1−y
C
y
have been proposed and prototypes thereof have been fabricated. The HBT of Si/Si
1−x
Ge
x
type, among others, is considered promising. As one reason, the band gap can be continuously tuned by utilizing the property that Si and Ge can form an almost complete solid solution together and the property that the band gap changes by applied strain. In order to utilize this advantage, there have been made many proposals on SiGe-BiCMOS devices including Si-MOSFET and HBT of a Si/Si
1−x
Ge
x
type formed on a common Si substrate.
In such proposals on SiGe-BiCMOS devices, MOSFET and HBT are generally formed simultaneously. By the simultaneous formation, the process can be simplified. For example, the gate insulating film of the MOSFET can be utilized as a layer for defining the collector opening of the HBT, and the gate electrode of the MOSFET and the base electrode of the HBT can be formed by patterning a common polysilicon film.
For enhancing the performance of MOSFET, high-temperature annealing is required. In the simultaneous formation of MOSFET and HBT described above, however, the annealing temperature must be controlled to avoid the performance of HBT from lowering. This may lower the performance of the MOSFET. Actually, when the performance of the MOSFET of the SiGe-BiCMOS device is compared with that of MOSFET of a standard CMOS device under the same design rule, it has been found that the former is inferior to the latter.
In order to form a high-performance SiGe-BiCMOS device, therefore, it is now considered advantageous to first form MOSFET requiring a high annealing temperature and thereafter form HBT. Also considered advantageous is that since Ge is a contaminant for a standard CMOS device fabrication line, HBT should preferably be formed separately from the MOSFET fabrication process in order to prevent Ge from being mixed in the MOSFET. In particular, if a dedicated fabrication line is not prepared for SiGe-BiCMOS devices, the fabrication process of MOSFET should be definitely separated from that of HBT. In consideration of the above, the procedure of forming first MOSFET and thereafter HBT, not forming MOSFET and HBT simultaneously, would be advantageous in the fabrication process of SiGe-BiCMOS devices.
FIG. 12
is a cross-sectional view of HBT formed in the procedure of forming first MOSFET and thereafter HBT in the conventional fabrication process of SiGe-BiCMOS devices. Referring to
FIG. 12
, the upper portion of Si (001) substrate
500
constitutes a retrograde well
501
having a depth of 1 &mgr;m that contains n-type impurities such as phosphorous introduced therein by epitaxial growth, ion implantation, or the like. The density of the n-type impurities in the surface portion of the Si substrate
500
is adjusted to about 1×10
17
atoms·cm
−3
. As device isolation, there are provided a shallow trench
503
filled with silicon oxide and a deep trench
504
composed of an undoped polysilicon film
505
and a silicon oxide film
506
surrounding the undoped polysilicon film
505
. The depth of the shallow trench
503
is about 0.35 &mgr;m and that of the deep trench
504
is about 2 &mgr;m.
A collector layer
502
is located in the region of the Si substrate
500
sandwiched by the adjacent trenches
503
. An n
+
collector drawing layer
507
is located in the region of the Si substrate
500
isolated from the collector layer
502
by the shallow trench
503
for connection of the collector layer
502
to an electrode via the retrograde well
501
.
A first oxide film
508
having a thickness of about 30 nm is provided on the Si substrate
500
. A collector opening
510
is formed through the first oxide film
508
. A Si/Si
1−x
Ge
x
layer
511
a
is formed on the portion of the surface of the Si substrate
500
exposed inside the collector opening
510
. The Si/Si
1−x
Ge
x
layer
511
a
is composed of a p-type impurity doped Si
1−x
Ge
x
layer having a thickness of about 60 nm and a Si layer having a thickness of about 10 nm. The lower portion of the center of the Si/Si
1−x
Ge
x
layer
511
a
(the center corresponds to the lower region of a base opening
518
to be described later) serves as an internal base
519
, while the upper portion of the center of the Si/Si
1−x
Ge
x
layer S
11
a
serves as an emitter layer.
A second oxide film
512
having a thickness of about 30 nm is provided as an etch stopper on the Si/Si
1−x
Ge
x
layer
511
a
and the first oxide film
508
. The second oxide film
512
has base junction openings
514
and the base opening
518
. A p
+
polysilicon layer
515
having a thickness of about 150 nm is provided over the second oxide film
512
burying the base junction openings
514
, and a third oxide film
517
is formed on the p
+
polysilicon layer
515
. The portion of the Si/Si
1−x
Ge
x
layer
511
a
excluding the lower region of the base opening
518
and the p
+
polysilicon layers
515
constitute an external base
516
.
An opening is formed through the p
+
polysilicon layer
515
and the third oxide film
517
at a position located above the base opening
518
of the second oxide film
512
. Fourth oxide films
520
having a thickness of about 30 nm are formed on the side faces of the p
+
polysilicon layer
515
. On the fourth oxide films
520
, sidewalls
521
made of polysilicon having a thickness of about 100 nm are formed. An n
+
polysilicon layer
529
is provided on the third oxide film
517
burying the base opening
518
. The n
+
polysilicon layer
529
serves as an emitter drawing electrode. The fourth oxide films
520
electrically isolate the p
+
polysilicon layer
515
from the n
+
polysilicon layer
529
, as well as blocking the impurities in the p
+
polysilicon layer
515
from diffusing to the n
+
polysilicon layer
529
. The third oxide film
517
electrically isolates the upper surface of the p
+
polysilicon layer
515
from the n
+
polysilicon layer
529
.
Ti silicide layers
524
are formed on the surfaces of the collector drawing layer
507
, the p
+
polysilicon layer
515
, and the n
+
polysilicon layer
529
. The outer side faces of the n
+
polysilicon layer
529
and the p
+
polysilicon layer
515
are covere
Asai Akira
Hara Yoshihiro
Ichikawa Yo
Kanzawa Yoshihiko
Katayama Koji
Nelms David
Nhu David
Nixon & Peabody LLP
Studebaker Donald R.
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