Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-11-08
2001-02-06
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S221000, C438S142000, C438S233000, C438S523000, C438S584000, C438S624000
Reexamination Certificate
active
06184071
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device which can improve an isolation characteristic and prevent a leakage current in conducting a borderless process, and a method for fabricating the same.
2. Background of the Related Art
A related art method for fabricating a semiconductor device will be explained with reference to the attached drawings. FIGS.
1
A~
1
G illustrate sections showing the steps of a related art method for fabricating a semiconductor device.
Referring to
FIG. 1A
, the related art method for fabricating a semiconductor device starts with depositing an initial oxide film
2
and a nitride film
3
on a semiconductor substrate
1
having an active region and a field region defined thereon. As shown in
FIG. 1B
, the nitride film is subjected to selective patterning to expose the initial oxide film
2
in the field region.
Then the patterned nitride film
3
is used as a mask to etch the semiconductor substrate
1
to form trenches therein. The trenches may be formed by coating a photoresist film on an entire surface, patterning the photoresist film to expose the field region, and etching the semiconductor substrate
1
. Then, a first oxide film
4
is deposited in the trenches by thermal oxidization. A buried insulating film is then deposited on an entire surface and etched by chemical mechanical polishing or etch back, to planarize the buried insulating film and the nitride film
3
, thereby forming a trench isolation region
5
projected from an upper plane of the semiconductor substrate, as shown in FIG.
1
C.
Then, as shown in
FIG. 1D
, the nitride film
3
and the initial oxide film
2
on the active region are removed.
As shown in
FIG. 1E
, a gate oxide film
6
is formed on the exposed active region, and a polysilicon layer
7
is deposited on an entire surface for forming a gate electrode. This can result in local recesses
13
at edges of a trench region caused by too much insulating film being removed by wet etching conducted before the gate oxide film is formed. This causes a gate-wraparound in which a recess portion at an edge in the active region is wrapped around by the gate electrode.
As shown in
FIG. 1F
, a mask for forming a gate is used in patterning the polysilicon layer
7
and the gate oxide film
6
, to form a stack of a gate electrode
8
and a gate oxide film
6
. The semiconductor substrate
1
on both sides of the gate electrode
8
is lightly doped with impurity ions. Then, an oxide film or a nitride film is deposited on an entire surface and etched back, to form sidewall spacers
9
at sides of the gate electrode
8
and the gate oxide film
6
. Then the semiconductor substrate
1
on opposite sides of the sidewall spacers
9
, excluding a portion under the gate electrode
8
, is heavily with impurity ions, to form LDD source/drain regions
10
.
Then, as shown in
FIG. 1G
, a planar protection film
11
is deposited on an entire surface. Then a contact hole is formed to each of the source/drain regions
10
, and a contact plug
12
is formed in each of the contact holes. In
FIG. 1G
, if the contact holes are misaligned so that the trench isolation region
5
is reached in addition to reaching the source/drain region
10
. Then the problem arises that the contact plug
12
will also make in contact with the semiconductor substrate
1
at an interface of the active region and the field region.
The aforementioned related art method for fabricating a semiconductor device has the following problems.
First, the thin gate oxide film, formed at recess portion
13
, shortens a device lifetime because the gate oxide film is susceptible to loss.
Second, as a thickness of the gate oxide film in a recess region becomes thinner due to loss of an edge portion in a trench isolation region, the device becomes more likely to degrade due to an inverse narrow width effect in which a threshold voltage decreases as a width of the gate is reduced.
Third, a short between the contact plug and the semiconductor substrate occurs when the contact hole is misaligned to reach to the field region, which causes a leakage current.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a semiconductor device and a method for fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a semiconductor device and a method for fabricating the same, which can improve a device isolation and a contact characteristics.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the semiconductor device includes a semiconductor substrate having an active region and a field region defined thereon, a bilayered gate electrode formed in one direction on the active region, a trench formed in the field region, an isolation region formed in, and on the trench to form a step to the semiconductor substrate so as to be projected from the semiconductor substrate, an insulating film barrier formed along a boundary of the active region projected from the semiconductor substrate, impurity regions in the semiconductor substrate in the active region on both sides of the gate line, a planar protection film having contact holes to the impurity regions on both sides of the active region, and a contact plug formed in each of the contact holes.
In another aspect of the invention, as embodied and broadly described herein, a semiconductor trench structure comprises a substrate being divided into active and field regions where a trench is formed in the field region, a surface film formed along a surface of the trench, and a barrier structure formed over edges of the trench.
In other aspect of the present invention, there is provided a method for fabricating a semiconductor device, comprising the steps of (1) defining an active region and a field region on a semiconductor substrate, (2) depositing a first insulating film on the semiconductor substrate, and forming a second insulating film pattern on the field region, (3) forming sidewall spacers at sides of the second insulating film pattern, (4) removing the first insulating film to expose the semiconductor substrate in the active region, and forming a gate insulating film, (5) forming a planar first conduction layer on the active region to a height identical to the second insulating film pattern, (6) forming a third insulating film on the first conduction layer on the active region, (7) removing the first insulating film and the second insulating film on the field region, (8) forming a trench in the field region, (9) forming a fourth insulating film in the trench, (10) forming a buried insulating film on an entire surface of a resultant body, (11) planarizing the buried insulating film, the fourth insulating film, the first conduction layer and the sidewall spacers, to leave the first conduction layer on the active region and the sidewall spacers at a boundary of the active region and the field region, and for the buried insulating film on the trench to form a step to the semiconductor substrate, (12) forming a second conduction layer on an entire surface, and etching the first conduction layer and the second conduction layer to form the gate electrode on the active region, (13) forming impurity regions in the active region on both sides of the gate electrode, (14) forming a planar protection film to have contact holes to the impurity regions, and (15) forming a contact plug in each of the contact holes.
It is to be
Hyundai Electronics Industries Co,. Ltd.
Lee Granvill D
Smith Matthew
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