Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-08-03
2004-02-03
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S381000, C438S255000, C438S398000
Reexamination Certificate
active
06686234
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, specifically to a semiconductor device including a capacitor having the surface of the electrode roughened, and a method for fabricating the semiconductor device.
A DRAM (Dynamic Random Access Memory) is a semiconductor device which can be formed of one transistor and one capacitor. Various studies have been so far made of structures of such semiconductor device which are denser and more integrated, and also methods for fabricating the semiconductor device of such structures.
Recently, as a structure which provides a larger storage capacitance for a cell area unchanged, a structure including the storage electrode formed of polycrystalline silicon film having the rugged surface (rugged polycrystalline silicon film) is proposed, and various studies are made of such semiconductor device.
A structure of the conventional semiconductor device using rugged polycrystalline silicon film will be explained with reference to
FIGS. 21A-21C
,
22
A-
22
B and
23
A-
23
B.
First, a transfer transistor is formed on a silicon substrate
100
in a device region defined by a device isolation film
102
. The transfer transistor comprises a gate electrode
106
formed through a gate insulation film
104
on the silicon substrate
100
, and a source/drain diffused layer
108
,
110
in the silicon substrate
100
on both sides of the gate electrode
106
(FIG.
21
A).
Then, BPSG film is deposited by, e.g., CVD method on the silicon substrate
100
with the transfer transistor formed on to form an inter-layer insulation film
112
of the BPSG film.
Next, a contact hole
114
which is opened onto the source/drain diffused layer
108
of the transfer transistor is formed in the inter-layer insulation film
112
by the usual lithography and etching (FIG.
21
B).
Then, a doped amorphous silicon film
116
is deposited on the entire surface by, e.g., CVD method (FIG.
21
C).
Then, the doped amorphous silicon film
116
is patterned by the usual lithography and etching to form a storage electrode
118
(FIG.
22
A).
Next, a rugged polycrystalline silicon film
120
is deposited on the entire surface by e.g., CVD method (FIG.
22
B).
Then, the rugged polycrystalline silicon film
120
is etched back by anisotropic etching using chlorine (Cl
2
) as an etching gas. The rugged polycrystalline silicon film
120
on the inter-layer insulation film
112
is removed.
At this time the rugged polycrystalline silicon film
120
on the storage electrode
118
is concurrently removed. However, a surface contour of the rugged polycrystalline silicon film
120
is reflected on the surface of the storage electrode
118
. The rugged polycrystalline silicon film
120
remains on the side wall of the storage electrode
118
.
Thus, the storage electrode
118
has the rugged surface and has the rugged polycrystalline silicon film
120
formed on the side walls thereof (FIG.
23
A).
Then, a silicon nitride film is deposited on the entire surface by, e.g., CVD method to form a dielectric film
122
of the silicon nitride film.
Next, a doped amorphous silicon film, for example, is deposited on the entire surface by, e.g., CVD method to form a cell plate electrode
124
of the doped amorphous silicon film.
Thus, a capacitor formed of the storage electrode
118
, the dielectric film
122
and the cell plate
124
is formed (FIG.
23
B).
Thus, a DRAM including the transfer transistor, and a capacitor having the rugged storage electrode is fabricated.
However, the above-described conventional method for fabricating the semiconductor device often causes decrease of a capacitance to a device structure having high aspect ratio of a space between the storage electrodes
118
. That is, when an aspect ratio of the space between the storage electrodes
118
is high, an etching rate at the space between the storage electrodes
118
is lowered due to the micro loading effect. In order to completely remove the rugged polycrystalline silicon film
120
between the storage electrodes
118
, more etching time is required. Too much etching time decreases a film thickness of the storage electrodes
118
. Consequently, the storage electrodes
118
have decreased surface areas, which leads to the capacitance decrease.
In order to depress the capacitance reduction, it is necessary that a doped amorphous silicon film
116
which is to form the storage electrodes are made thicker in advance. However, it makes time of forming the storage electrodes
118
longer and makes it difficult to condition the etching for forming the storage electrodes
118
. Furthermore, it more burdens the system for fabricating the semiconductor device.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device and a method for fabricating the semiconductor device which permits the surface of the storage electrodes rugged without decreasing a capacitance and complicating the fabrication steps.
The present invention is characterized mainly in that, in etching back the polycrystalline silicon film having the rugged surface (hereinafter called rugged polycrystalline silicon film (which is also called as a HSG (Hemispherical Grain))), an etching gas including a halogen based gas and O
2
gas and etching conditions which make the deposition relatively strong with respect to the etching are used. The etching back of the rugged polycrystalline silicon film under such conditions is applied to, e.g., a method for forming a storage electrode having the rugged surface, whereby the storage electrode can have a surface area increased without sacrificing a height of the storage electrode.
The principle of the present invention will be explained by means of an example that the present invention is applied to the etching back of the rugged polycrystalline silicon film formed on the storage electrode pattern.
Generally, the etching process of reactive ion etching is a competing reaction between the deposition and the etching. Here, the deposition is caused by adsorption of neutral radicals, and the etching is caused mainly by ions as an etchant. Respective movements of the radicals and the ions will be explained. The radicals, which are electrically neutral, are isotropic in their moving direction. The ions, which are charged, are anisotropic in the vertical direction of a wafer because the ions are attracted by a plasma sheath voltage. Accordingly, when the etching process is considered in a region of a high aspect ratio, the anisotropic ions are easier to enter the space than the radical, so that the micro loading effect of the radicals is occurred prior to that of the ions. When the space has a small width, the micro loading effect that the ions and the radicals cannot easily enter the space, and the etching rate is low is caused. However, as shown in
FIGS. 1A and 1B
, in terms of incidence amounts of the ions and those of the radicals, space widths for causing the micro loading effect are different from each other. Resultantly, as a space width is decreased, an etching rate once increases in a certain region due to the micro loading effect of the radicals, and then decreases due to the micro loading effect of the ions (FIG.
1
C).
The present invention utilizes different space widths for causing the micro loading effect of the ions and the radical so as to control the etching.
In the present invention, conditions using a etching gas including halogen based gas and O
2
gas, which make the deposition stronger are used for etching back the rugged polycrystalline silicon film. Here, conditions for making the deposition stronger mean conditions under which the deposition is relatively strong with respect to the etching. In terms of oxygen flow rates, the conditions may be said to be conditions under which an oxygen gas ratio for causing the deposition is high.
In the initial stage of the etching, i.e., in the stage where the rugged polycrystalline silicon film is present on the entire surface of a wafer, the oxygen in the etching gas is used for the etching on the entire
Armstrong Kratz Quintos Hanson & Brooks, LLP
Fujitsu Limited
Pham Long
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