Semiconductor device and method for fabricating the same

Details Semiconductor device and method for fabricating the same Semiconductor device and method for fabricating the same

2002-08-16

2003-09-30

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S217000, C438S231000

Reexamination Certificate

active

06627490

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device in which memory cells and peripheral circuits (core) thereof are provided on the same substrate; and a method for fabricating such a device. More particularly, the present invention relates to a semiconductor device having a reduced area occupied by the core section and an improved operating speed; and a method for fabricating such a device.
2. Description of the Related Art
In recent years, the degree of integration of a semiconductor device has been increased. In a system-on-chip (SOC) device, memory cells and peripheral circuits (core) such as a central processing unit (CPU) for controlling the operation of the memory cells are formed on the same substrate. In such a SOC device, the memory cells are required to stably maintain data therein even when an &agr; ray is incident thereon, i.e., to have a soft error resistance, and the core is required to increase the operating speed of logical circuits thereof. Therefore, in the case where the memory cells form an SRAM (static random access memory), it is necessary to increase the source-drain junction capacitance of each CMOS (complementary metal-oxide semiconductor) transistor in the SRAM section, while decreasing the source-drain junction capacitance of each CMOS transistor in the core section.
However, the following problems arise when an impurity concentration of a well of each circuit in the core section is reduced in order to reduce the junction capacitance in the core section. Each of FIG.
1
A and
FIG. 1B
shows a cross-sectional view illustrating punch-through occurring under a device separation region in a conventional CMOS transistor. As shown in FIG.
1
A and
FIG. 1B
, in the CMOS transistor, a p-well
83
and an n-well
84
are provided on the surface of a semiconductor substrate
81
and separated from each other by a device separation film
82
. The CMOS transistor includes an n-channel MOS transistor
87
and a p-channel MOS transistor
88
. The n-channel MOS transistor
87
includes an n
+
-source diffusion layer
85
a
and an n
+
-drain diffusion layer
85
b
provided at the surface of the p-well
83
. The p-channel MOS transistor
88
includes a p
+
-source diffusion layer
86
a
and a p
+
-drain diffusion layer
86
b
provided at the surface of the n-well
84
.
Moreover, a p
+
-well contact layer
91
isolated from the n
+
-source diffusion layer
85
a
by an insulating film
89
is provided at the surface of the p-well
83
, and an n
+
-well contact layer
92
isolated from the p
+
-source diffusion layer
86
a
by an insulating film
90
is provided at the surface of the n-well
84
.
In the thus-structured CMOS transistor, when 0(V) is applied to gate electrodes
93
and
94
, 1.8(V) to the n
+
-drain diffusion layer
85
b
and the p
+
-drain diffusion layer
86
b
, 0(V) to the n
+
-source diffusion layer
85
a
and the p
+
-well contact layer
91
, and 1.8(V) to the p
+
-source diffusion layer
86
a
and the n
+
-well contact layer
92
, as shown in
FIG. 1A
, punch-through between the p
+
-drain diffusion layer
86
b
and the p
+
-well contact layer
91
is likely to occur under the device separation film
82
and the insulating film
89
via the n-well
84
and the p-well
83
.
When 1.8(V) is applied to the gate electrodes
93
and
94
, 0(V) to the n
+
-drain diffusion layer
85
b
and the p
+
-drain diffusion layer
86
b
, 0(V) to the n
+
-source diffusion layer
85
a
and the p
+
-well contact layer
91
, and 1.8(V) to the p
+
-source diffusion layer
86
a
and the n
+
-well contact layer
92
, as shown in
FIG. 1B
, punch-through between the n
+
-well contact layer
92
and the n
+
-drain diffusion layer
85
b
is likely to occur under the device separation film
82
and the insulating film
90
via the n-well
84
and the p-well
83
. Hereinafter, such punch-through is referred to as “well-to-well punch-through”.
When the impurity concentration of an area, e.g., a well, near the area where the source-drain diffusion layer of the CMOS transistor is to be formed is reduced in order to reduce the junction capacitance, punch-through is more likely to occur under the device separation region.
Conventionally, the above-described problem has been addressed as follows. In the core section, the impurity concentration of the well is reduced while increasing the width of the device separation film disposed between the pMOS and the nMOS which together form the CMOS. FIG.
2
A and FIG.
2
B through FIG.
12
A and
FIG. 12B
show cross-sectional views sequentially illustrating the steps of a conventional method for fabricating a semiconductor device. In these figures, each of FIG.
2
A through
FIG. 12A
shows a region corresponding the core section of the semiconductor device, and each of FIG.
2
B through
FIG. 12B
shows a region corresponding to the SRAM section of the semiconductor device.
First, as shown in FIG.
2
A and
FIG. 2B
, a p
−
-epitaxial layer
52
is formed on a p-type silicon substrate
51
in both of the core section and the SRAM section. Next, in the core section, a device separation film
53
a
is formed in a predetermined area at the surface of the p
−
-epitaxial layer
52
, and in the SRAM section, a device separation film
53
b
is formed in a predetermined area at the surface of the p
−
-epitaxial layer
52
. As a result, the core section is defined into an nMOS region
111
where an n-channel MOS transistor is to be formed, and a pMOS region
112
where a p-channel MOS transistor is to be formed. The SRAM section is defined into an nMOS region
113
where an n-channel MOS transistor is to be formed, and a pMOS region
114
where a p-channel MOS transistor is to be formed. The width of the device separation film
53
a
is, for example, 1.2 &mgr;m, and the width of the device separation film
53
b
is, for example, 0.4 &mgr;m. Thereafter, a sacrificial oxide film (not shown) is formed over the entire surface of the device.
Next, as shown in FIG.
3
A and
FIG. 3B
, a resist
54
including an opening
54
a
is formed. The opening
54
a
extends over the nMOS region
111
and a part of the device separation film
53
a
which is closer to the nMOS region
111
, and the resist
54
completely covers the SRAM section. The size of a portion of the opening
54
a
which is located over the device separation film
53
a
is about a half of the size of the device separation film
53
a
. Next, B
+
ions are implanted using the resist
54
as a mask with an acceleration voltage of 300 keV and a dose of 1.5×10
13
, for example. Thus, in the core section, a p-type well
55
which is deeper than the device separation film
53
a
is formed in the p
−
-epitaxial layer
52
.
As shown in FIG.
4
A and
FIG. 4B
, a resist
56
including an opening
56
a
is formed after removing the resist
54
. The opening
56
a
is provided in the center of the nMOS region
111
, and the resist
56
completely covers the SRAM section. Next, B
+
ions are implanted using the resist
56
as a mask with an acceleration voltage of 30 keV and a dose of 8×10
12
, for example, so as to form a p-type channel
57
at an intermediate depth of the p
−
-epitaxial layer
52
.
As shown in FIG.
5
A and
FIG. 5B
, a resist
58
including an opening
58
a
is formed after removing the resist
56
. The opening
58
a
extends over the nMOS region
113
and a part of the device separation film
53
b
which is closer to the nMOS region
113
, and the resist
58
completely covers the core section. Next, in the SRAM section, B
+
ions are implanted using the resist
58
as a mask, for example, with an acceleration voltage of 150 keV and a dose of 2×10
13
, so as to form a p-type well
59
in the p
−
-epitaxial layer
52
. Moreover, B
+
ions are implanted using the resist
58
as a mask, for example, with an acceleration voltage of 30 keV and

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