Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-06-29
2003-09-09
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000, C438S183000, C438S290000, C438S259000, C438S589000, C257S288000, C257S330000
Reexamination Certificate
active
06617212
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and methods for fabricating semiconductor devices, and more particularly, to semiconductor devices fabricated using a damascene process and methods for fabricating semiconductor devices using a damascene process.
2. Description of Related Art
Generally, as an integration density of a semiconductor device gradually increases, the use of a semiconductor integration technology implementing a damascene process becomes more desirable.
For example, in a semiconductor fabrication process using a metal film as a gate electrode material, the use of the damascene process forms a gate electrode following the formation of a gate pattern and a source/drain region. The process reduces semiconductor substrate loss caused by thermal budgets and plasma. In addition, the use of the damascene process eliminates an oxidation process; therefore, generation of gate electrode defects caused by an oxidation process do not occur.
FIGS. 1A-1E
illustrate a known method for forming a gate electrode using a damascene process.
As illustrated in
FIG. 1A
, a dummy gate insulating film
2
and a dummy gate film
3
are sequentially deposited on a surface of a semiconductor device
1
having a device isolation film. Thereafter, a photoresist pattern
4
is formed on the dummy gate film
3
at a region intended for a gate electrode.
Next, as shown in
FIG. 1B
, the dummy gate film
3
and the dummy gate insulating film
2
are sequentially etched using the photoresist pattern
4
as a etch barrier, thereby forming a dummy gate electrode
5
. The etching process for forming the dummy gate electrode
5
allows a portion of the dummy gate insulating film
2
on the substrate
1
to remain intact.
Then, ions, for example, low concentration n-type impurity ions are implanted into the resulting substrate to form an LDD
6
, after which the photoresist pattern
4
is removed. Thereafter, using a known process, spacers
7
are formed on both sidewalls of the dummy gate electrode
5
. Then, high concentration n-type impurity ions are implanted into an area reserved for a source/drain, and then the ions are activated by a thermal process to form a source/drain region
8
. Then, an interlayer insulating film
9
for insulating the respective devices is deposited on the resulting substrate.
Referring to
FIG. 1C
, the interlayer insulating film
9
is polished using Chemical Mechanical Polishing (CMP) to expose the dummy gate electrode
5
. The exposed dummy gate electrode
5
is then removed by a dry or wet etching process, thereby forming a groove
10
defining a region reserved for a gate electrode. When removing the dummy gate electrode to form the groove
10
, the insulation film
2
under the dummy gate film
3
and under a portion of the sidewalls
7
is etched, which forms edges
2
a.
Next, as shown in
FIG. 1D
, a thermal oxide film is grown or a high dielectric film is deposited, on a surface of the groove
10
, thereby forming a gate insulating film
11
. Next, a doped polysilicon film or a metal film is deposited on the gate insulating film
11
to completely fill the groove
10
. As a result, a gate electrode
12
is formed.
The fabricating method of the semiconductor device using the above-described damascene process suffers from the following disadvantages.
As disclosed, the dummy gate electrode and the dummy gate insulating film are removed in sequence to form the groove
10
. The process of forming the groove
10
requires the formation of the edges
2
a
. These edges
2
a
are recessed as illustrated in
FIG. 1C
as a result of the etching process. The etched edges
2
a
are portions that are influenced significantly by a hot carrier upon operation of a transistor. Moreover, the edges
2
a
significantly influence Gate Oxide Integrity (GOI). Therefore, the edges
2
a
may prevent the formation of the gate insulating film
11
. Moreover, even if the gate insulating film
11
is successfully formed, it will likely be weak. These factors deteriorate the reliability and productivity of the semiconductor device.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method for fabricating a semiconductor device using a damascene process, which prevents formation of recessed edges in a gate electrode region during etching, thus, improving the reliability of the gate electrode.
Another object of the present invention is to provide a semiconductor device fabricated using a damascene process, where the semiconductor device has improved gate electrode reliability.
In one embodiment, the present invention provides a method for fabricating a semiconductor device using a damascene process, including the steps of forming a dummy gate electrode on a semiconductor substrate having a device isolation film; wet-etching the dummy gate electrode to remove an oxide film on the dummy gate electrode; depositing an Al
2
O
3
film as a protective film over the semiconductor substrate; heat-treating the substrate on which the Al
2
O
3
was deposited; implanting low concentration impurity ions into the substrate to form a lightly doped drain (LDD) region; forming spacers on both sidewalls of the dummy gate; implanting high concentration impurity ions into the substrate to form a source/drain region; heat-treating the substrate to activate the implanted high concentration ions; forming an interlayer insulating film on the substrate; polishing and planarizing the interlayer insulating film using a Chemical Mechanical Polishing process to expose the dummy gate electrode; etching the dummy gate electrode and the dummy gate insulating film in sequence to form a groove defining a gate electrode forming region; depositing a gate insulating film on the surface of the groove; and depositing a doped polysilicon film or a gate metal film on the gate insulating film in the groove, thereby forming a gate electrode.
In another embodiment, the present invention provides a method for fabricating a semiconductor device using a damascene process, including the steps of depositing a dummy gate insulating film and a dummy gate electrode on a semiconductor substrate having a device isolation film; depositing an oxide film on over the semiconductor substrate using a LDD oxidation process; wet-etching the dummy gate electrode to remove an oxide film on the dummy gate electrode; depositing an Al
2
O
3
film as a protective film over the semiconductor substrate; heat-treating the substrate; implanting low concentration impurity ions into the substrate to form a LDD region; forming spacers on both sidewalls of the dummy gate electrode; implanting high concentration impurity ions into the substrate to form a source/drain region; heat-treating the substrate to activate the high concentration impurity ions; forming an interlayer insulating film on the substrate; polishing and planarizing the interlayer insulating film using a Chemical Mechanical Polishing process to expose the dummy gate electrode; etching the dummy gate electrode and the dummy gate insulating film in sequence to form a groove defining a gate electrode region; depositing a gate insulating film on the surface of the groove; and depositing a doped polysilicon film or a gate metal film on the gate insulating film in the groove, thereby forming a gate.
In still another embodiment, the present invention provides a method of fabricating a semiconductor device using a damascene process, including the steps of depositing a dummy gate insulating film and a dummy gate electrode on a semiconductor substrate having a device isolation film; wet-etching the dummy gate electrode so as to remove an oxide film on the dummy gate electrode; depositing an AlON film over the semiconductor substrate; heat-treating the substrate to transform the AlON film into an Al
2
O
3
film; heat-treating the substrate on which the Al
2
O
3
was formed; implanting low concentration impurity ions into the substrate to form a LDD region therein; forming spacers on both sidewalls of the dummy gate; i
Cho Heung Jae
Park Dea Gyu
Birch & Stewart Kolasch & Birch, LLP
Luu Chuong A
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