Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-06-05
2007-06-05
Decady, Albert (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C713S176000
Reexamination Certificate
active
10337665
ABSTRACT:
A semiconductor device includes at least one component which is vulnerable to damage during scan testing for a particular input data configuration, and supports a safe mode in which this particular input data configuration is disabled. The semiconductor device also includes a port for receiving an input scan vector for scan testing, and an authorization unit connected to said port. The authorization unit maintains the device in safe mode if an input scan vector does not satisfy at least one predetermined criterion. In one particular implementation, the authorization unit generates a digital signature for the input scan vector, which is then compared to a signature portion included within the input scan vector itself. Scan testing is enabled providing that this comparison finds a match.
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House Kenneth Alan
Siegel Joseph Raymond
Williams Emrys
De'cady Albert
Kowert Robert C.
Meyertons, Hood, Kivlin, Kowert & Goetzel, P. c.
Sun Microsystems Inc.
Tabone, Jr. John J.
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